Re: Constrain SDR source-synchronous bidirectional interface

Altera_Forum · ‎03-02-2017

I need to interface an MAX10 to an 16-bit external memory bus of MCU. All signals are synchronous to the 100MHz internal clock of the MCU (obviously) and a 25MHz submultiple of said clock is output alongside the bus signals into the PLL of the MAX10. The signals as seen from the FPGA are as follows:

SCK input, 25 MHz clock, edge-aligned to all other signals

nWE input, write access

nOE input, read access

nADV input, address valid

AD[0..15] bidir, multiplexed address and data

Opertation of the interface is as follows; The MCU

1. asserts nADV and outputs the address on AD, then either

2a asserts nWE and presents the data on AD, or

2b asserts nOE and expects the output from the MAX10 on AD some cycles later.

The length of the address and read/write data phase can be adjusted in multiples of the 100MHz MCU clock.

My idea was to multiply the input SCK with the PLL of the MAX10 set to source-synchronous compensation mode and let the fitter figure out the necessary phase shift. I've got the following timing constraints defined:


#  virtual 100Mz clock and 25MHz input clock
create_clock -name fsmc_vsck -period 10.000
create_clock -name {fsmc_sck} -period 40.000 
#  derive clocks produces a 100MHz clock that feeds the interface controller
derive_pll_clocks
derive_clock_uncertainty
#  Board delays tpd estimated by taking trace length difference relative to clock trache and 170ps/inch#    tpd,min= -0.05ns (data trace shorter than clock trace) #    tpd,max = 0.1ns (data trace longer than clock trace)
#  input delays for tco (clock-edge to output) as specified by MCU#    tpd,min= -0.05ns and tpd,max = 0.1ns#    tco,min=0 and tco,max=2ns# #  input delay max = tpd,max + tco,max#  input delay min = tpd,min + tco,min# 
set_input_delay -add_delay -max -clock   2.100 }]
set_input_delay -add_delay -min -clock   -0.050 }]
... for all input signals ....
#  output delays for tsu (data-setup before clock edge) and th (data-hold after clock edge)#    tsu=1.5ns#    th=1ns# #  output delay max= tpd,max + tsu#  output delay min = tpd,min - th# 
set_output_delay -add_delay -max -clock   1.600 }]
set_output_delay -add_delay -min -clock   -1.050 }]
... for all output signals ...

Furthermore, I have set fast input/output registers on all bus signals via:


attribute useioff : boolean;
attribute useioff of nEN : signal is true;

And I have set PLL compensation on all bus pins via:

set_instance_assignment -name PLL_COMPENSATE ON -to fsmc*

However, I get timing errors for slow and fast models for both phase shift of 0° and 90°. Am I missing something?

Altera_Forum · ‎03-02-2017

I don't see a generated output clock for the output interface. Using derive_pll_clocks is OK, but you still need a generated clock on the clock output port (and an associated false path for that output clock so it's not analyzed as a data path). The output delay constraints should reference this newly generated output clock, not an input clock. Also, you reference clocks named fsmc_vsck and fsmc_sck in the input/output delay constraints, but you named them just vsck and sck. Check your ignored constraints report because I'm betting it will list these as ignored.

Constraining source synchronous manually is a beast. Check out this online training and see if you're missing anything.

https://www.altera.com/support/training/course.html?coursecode=ocss1000

Altera_Forum · ‎03-03-2017

I've corrected the type in the clock constaints - they were correct in the original sdc.

One clarification: there is no output clock from the MAX10 to the MCU. Instead , the MCU supplies a constant 25MHz clock to which the data and control lines are synchronous both for writes (data from MCU to FPGA) and reads (data driven by FPGA).