Constraining SPI flash lines

[maitreya_ranade]

I am trying to constrain Flash SPI lines. These are my specifications:

FPGA Clock: 100MHz (Derived from PLL)

SPI Clock: 50Mhz

SPI Master: FPGA

SPI Clock generation: FPGA

The FPGA is using the generated SPI clock to clock in the data back from the slave

I have following questions:

• How do I constrain MISO, MOSI & SCLK signals?
• How to configure set_input_delay constraint for MISO?
• How to configure set_output_delay constraint for MOSI?
• Do I need to constrain SCLK as well?
• Where to find flash device Tco?

[KennyTan_Altera]

Here is some example that you can try:

# === Clocks ===

# 100 MHz board/system clock (ns, not MHz)

create_clock -name CLK_IN -period 10.000 [get_ports {clk}]

# PLL output at 100 MHz (adjust instance path as needed)

create_generated_clock -name PLL_100M \

 -source [get_ports {clk}] \

 [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}]

# Clock on the SPI SCLK output pin (this is the reference we'll use)

# Use the PLL output (or the clock that actually feeds your SCLK generator) as -source

create_generated_clock -name SCLK_FPGA \

 -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] \

 [get_ports {SCLK1}]

# (If your SCLK port is QSPI_CLK, change {SCLK1} to {QSPI_CLK})

# === Board delays & flash timing (example numbers; replace) ===

# PCB delay from FPGA pins to device pins (ns)

set sclk_board 0.80

set mosi_board 0.70

set miso_board 0.95

# Relative skews (ns)

set skew_out [expr {$sclk_board - $mosi_board}] ;# SCLK vs MOSI at the device

set skew_in [expr {$miso_board - $sclk_board}] ;# MISO vs SCLK at the FPGA

# Flash datasheet timing (ns) — replace with your part’s values

set t_su   2.5  ;# flash input data setup to SCLK sampling edge

set t_h   1.0  ;# flash input data hold from SCLK sampling edge

set tco_min 1.5  ;# flash SCLK→MISO earliest

set tco_max 6.0  ;# flash SCLK→MISO latest

# === MOSI (FPGA -> Flash) ===

# If the flash samples MOSI on RISING SCLK: (SPI mode accordingly)

set_output_delay -clock [get_clocks SCLK_FPGA] \

 -max [expr {$t_su + $skew_out}] [get_ports {MOSI1}]

set_output_delay -clock [get_clocks SCLK_FPGA] \

 -min [expr {-$t_h + $skew_out}] [get_ports {MOSI1}]

# If the flash instead samples on FALLING SCLK, add -clock_fall to BOTH lines above:

# set_output_delay -clock [get_clocks SCLK_FPGA] -clock_fall -max ...

# set_output_delay -clock [get_clocks SCLK_FPGA] -clock_fall -min ...

# === MISO (Flash -> FPGA) ===

# If the flash launches MISO on the OPPOSITE edge to the MOSI sampling edge (typical),

# use -clock_fall. If it launches on rising, omit -clock_fall.

set_input_delay -clock [get_clocks SCLK_FPGA] -clock_fall \

 -max [expr {$tco_max + $skew_in}] [get_ports {MISO1}]

set_input_delay -clock [get_clocks SCLK_FPGA] -clock_fall \

 -min [expr {$tco_min + $skew_in}] [get_ports {MISO1}]

# === Good practice ===

derive_pll_clocks

• derive_clock_uncertainty

Notes:

Don’t put set_output_delay on SCLK1 itself—SCLK is the reference clock, not data.

Use -clock_fall on MOSI/MISO constraints if your SPI mode uses the falling edge for sampling/launching.

Replace {SCLK1}, {MOSI1}, {MISO1} (or {QSPI_CLK}) and the PLL path with your actual names, and plug in your flash datasheet timings and measured PCB delays.

[KennyTan_Altera]

Not sure if you have further question for the above? If no, we shall close this thread.

[KennyTan_Altera]

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