Timing constraints can be verified by going through synthesis (standard edition) or the plan stage (pro edition) and then creating a netlist in the timing analyzer based on that stage of compilation. Then you'd generate timing reports as usual, though note that the results should not be used as final timing numbers due to further optimizations that may be performed by the Fitter.
For pins, you can run an I/O Assignment Analysis from the Processing menu at any time. It will run the Fitter enough to get to the point where the I/O is analyzed without going through a full fit.
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