I am new to the Altera Quartus software tool.So Please anyone guide me to accomplish my task.
Design Process involves:
1. Need to compile 8-bit, or 32-bit or 64-bit counter in Quartus
2. Interconnect the counter module with NIOS using SOPC
3. Want to see counter result in NIOS console
For above design, i Have followed the below step but in NIOS data is not printing in proper sequence (randomly printing). I dont know why ?
VERILOG code
SUB-MODULE
module counter
(
input clk, enable, rst_n,
output reg[7:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule module Counter_Top_Level_design
(
input clk,
input rst_n,
output [7:0] out
);
wire counter_enable;
counter counter_inst (
.clk ( clk ),
.rst_n ( rst_n ),
.enable ( counter_enable ),
.count ( out )
);
// For simulation, use this instantiation:
NIOS_SYSTEM niosii_system_inst (
.clk_clk ( clk ), // clk.clk
.reset_reset_n ( rst_n ), // reset.reset_n
.enable_external_connection_export ( counter_enable ), // output_pio.export
.cout_export ( out )
);
endmodule
NIOS console
Link Copied
I have uploaded Qsys design too. Enable : PIO 1-bit (Output) and cout_export : PIO 8-bit Input
