Critical Warning: Timing requirements for slow timing model timing analysis were not

[Altera_Forum]

Hello, 

I'm trying out a Rs-232 Receiver and Transmitter code in Quartus || version 9.0 Build 235 06/17/2009 SJ full version, i ma getting a following critical warning during the compilation stage   critical warning: timing requirements for slow timing model timing analysis were not met. see report window for details.   and when i'm checking the compilation summary and timing analyser section i see the following data in the which is shownin pics below   picture of summary :     http://i1140.photobucket.com/albums/n569/Siva_Chaitanya/critwarn2.jpg    picture 2 :    http://i1140.photobucket.com/albums/n569/Siva_Chaitanya/critwarn1.jpg    please help me resolve this problem :confused:, i'm completly new to this situation   Cheers Siva

[Altera_Forum]

Have you added your sdc file to project to define timing constraints?

[Altera_Forum]

thanks for replying Kaz. 

 we haven't included as sdc file as such.   We were just asked to write the code and try to implement on fpga. they havent given any timing constraints except the operating clock frequency.

[Altera_Forum]

you need to add sdc file otherwise it defaults to some mystery violations... at least your clock frequency and io. look at examples of basic sdc in timequest resource centre altera website

[Altera_Forum]

we have added clock frequency by gng into edit settings and given value in individual clocks.. once we have done tht, we have got all these warnings..is it necessary to give the input delay for the design?

[Altera_Forum]

Are you using classic timing or timequest. Timequest needs sdc. 

Internal timing requires clock frequency but io then needs set delay constraints.

[Altera_Forum]

we are not using it Kaz. 

 fine we wil try to do give some delay constarints to io and chk.   and one more thing sir. can i use a synchroniser to maintain skew between the block.

[Altera_Forum]

For clock domain transfers (asynchronous signals) then you need synchronisers and set false path

[Altera_Forum]

actually our signals are synchronous. 

 In altera tool in the edit settings --> classic timing analyser settings  we have an option of giving delay time settings( tsu, tco, tpd, th). Is that enough if I give my values in that instead of including sdc?

[Altera_Forum]

If you switch to classic analyser then yes you can enter your clock(s) and tSU/tH/tCO and should be enough. You can also add cut paths, multicycle etc... through assignment editor per node.