VHDL type mismatch error

[Altera_Forum]

HI, 

I use am29lv065d flash to custmize my development board,but I got a error when ANALYSIS&SYNTHESIS   VHDL type mismatch error at am29lv065d.vhd(109):VitalDelayType type does not match string literal. and 109 line is: tdevice_POB :VitalDelayType :=5 us;--byte write  I also look up the datasheet file for tdevice_POB's value,it is surely 5us.  How can I solve this problem? tks!

[Altera_Forum]

Is the file your looking at meant for synthesis or for simulation? VHDL has a lot of features that are purely for simulation and not for synthesis. Any file I've ever seen with vital delays was made to be interpreted by a simulator and not for synthesis. If this is a flash model, then it's made to simulate your interface, but wouldn't actually get synthesized into the FPGA.

[Altera_Forum]

hi,Rysc, thanks for your reply. 

you mean this vhdl file is for simulation ,not for synthesis,and sysnthesis needs desigh vhdl file? if so , how can I get the design vhdl file for flash ,does the manufactrue provide ? I did't find in offical webiste.

[Altera_Forum]

Hi, David. I am learning to use flash in my design. Could you give me some your materials about flash? 

Thank you very much. Email：hapyang204@hotmail.com

[Altera_Forum]

I customize development board from scratch,could you give me some infomation or advices on how to make it.tks very much!!

[Altera_Forum]

Who's development board are you using? Does a sample design come with it that makes use of the flash? If so, I strongly recommend working from there, or at least studying it and integrating the design into your system. Are you using Nios, because there is common flash controller in the SOPC system. If you really want to build one from scratch, you can do that too(which is where the memory model is important, so you can simulate the functionality of your flash controller against a real memory model.)

[Altera_Forum]

Hi,Rysc 

I 'm not using any development board ,I just want to customize a development board by myself. because no development board meet my need is avaliable. so I should choose suitable componets, such as sdram ,cfi flash ,sram etc then connect them to the nios ii cpu which is generated by the sopc builder and then Analysis&Synthesis , Filter ,Time analyze,simulation and make sure every componet works well on the basis of nios ii. and then generate netlists of my customized board then make a board using the netlists  so I need the components desigh vhdl/verilog modules ,for examples: I using mt48lc4m32b2-7 sdram,so I get the mtmt48lc4m32b2-7 vhdl file,and change it to symbols file,and connect it to the nios ii cpu with sdram controller port to port, other components are in the same way this error is occured when I systhesis my customized board.  so would you give me some advices on how to customize a development board on the basis of nios ii in quartus. or give me some valuable meterials, tks very much!

[Altera_Forum]

I won't be of much help here, as I don't build SOPC/Nios systems, so maybe someone else can jump in. Note that the SOPC builder has a common flash interface controller: 

http://www.altera.com/literature/quartus2/lit-qts-peripherals.jsp And you might want to explain in more detail what you've done, as I'm not quite following. For example, you have a top-level system that is, or instantiates, an SOPC system with Nios. Are you then adding a flash controller and it's failing, or do you have source for a controller and are trying to make a peripheral? Etc.  (Also, another resource to look at is niosforum.com.)

[Altera_Forum]

Looks like you are missing the point here. Use Quartus II compilation only for the design that goes inside the FPGA, i.e., SOPC Builder system with Nios II processor. Not with the peripheral components that you would like to be present on the board surrounding the FPGA. From system's perspective, all of the peripheral components (like cfi flash, sram, sdram, etc.) are simulation models to Quartus II synthesis/simulation flow. The core controllers (instantiated in SOPC builder) are the actual synthesizable part that is to be used by Quartus II synthesis flow. The memory models can be used when you simulate your design in ModelSim or any other simulation tool.  

 Hope this will help.  -BD

[Altera_Forum]

I understand! tks to BD_SLS!

[Altera_Forum]

Hello to everybody. 

Please someone could tell me where is the error in the following VHDL code?   library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity round16to12 is    port   (  a : in std_logic_vector(15 downto 0);  q : out std_logic_vector(11 downto 0)  );  end entity;  architecture beh of round16to12 is  19 begin 20  21 process(a) 22 begin 23  24 q <= (11 => not(a(15)), others => a(14 downto 4) ); 25 end process; 26  27 end beh;    Quartus II 7.2 sp1 web edition gives me the following error:  Error (10381): VHDL Type Mismatch error at round16to12.vhd(24): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression  I really don't understand the reason of that message. Thanks for your support

[Altera_Forum]

Hello, 

 I think, line 24 makes wrong usage of others. It must have a bit value as argument here, '0', '1' or 'Z', it doesn't accept a bit vector.  I would use a concatenation instead: q <= not a(15) & a(14 downto 4) ;  Regards, Frank

[Altera_Forum]

Hello Frank, 

thank you very much for your support: it fixed my problem. Best Regards.

[Altera_Forum]

this post helped me alot !!!! 

Cheers