Curious optimization of a reset circuit

[AndrewH]

I have seen a number of posts about creating a suitable reset.

The attached notes shows one successful attempt (testcase-2).

However, I am at a loss as to why testcase-3 fails.

I thought I would share my thoughts and notes to see what further advice could be provided by the wider community.

All the notes are in a PDF document (because I've included some waveforms from the simulator ... of RTL and of post-synthesis Quartus-generated files)

Any thoughts would be most appreciated.

Thank you.

Andrew

[RichardTanSY_Intel]

I will need to discuss with the internal team related to the power-on-reset. Please allow me some time to work on it.

[RichardTanSY_Intel]

After discussion, we don't usually create POR as it is a part of the FPGA. 

I think the user guide below may help to explain how the power-on reset circuitry works in MAX10 fpga. 

Power-On Reset Circuitry 

Or you are asking about Asynchronous & Synchronous Reset design? Perhaps this paper may help to explain.  

http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf

[RichardTanSY_Intel]

Hi, 

We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Best Regards,

Shyan Yew