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run examples in quartus prime pro 20.2

Hi,

I installed the quartus prime pro 20.2 in my desktop. The OS is CentOS 7.2. I installed the device library Arria 10, Stratix 10, Agilex and the simulation tools is Modelsim ae. The installation is successful and licensed. But when I run the example on the hls\examples\tutorials\hls_float\1_reduced_double, errors occurred. The procedure is shown as follows.


[root@localhost 20.2]# cd hls
[root@localhost hls]# source init_hls.sh
[i] INFO:
Taking this script's directory as the root
of the Intel(r) HLS Compiler installation:
'/mnt/data/intelFPGA_pro/20.2/hls'

[i] INFO:
Quartus is available through your environment:
${_h_dir}/../quartus ->
/mnt/data/intelFPGA_pro/20.2/quartus
This setup will make it available on your PATH:
'/mnt/data/intelFPGA_pro/20.2/quartus/bin/quartus_sh'

[i] INFO:
Platform Designer was installed with Quartus.
This setup will make it available on your PATH:
'/mnt/data/intelFPGA_pro/20.2/qsys'

[i] INFO:
ModelSim is available on your PATH:
'/mnt/data/intelFPGA_pro/20.2/modelsim_ae/bin/vsim'

[i] INFO:
ModelSim simulator version:
Model Technology ModelSim - Intel FPGA Edition vsim 2020.1_3 Simulator 2020.04 Apr 27 2020

[i] INFO:
Found GCC Tool Chain in your installation directory:
'/mnt/data/intelFPGA_pro/20.2/gcc'

[i] INFO:
Setting up Intel(R) HLS Compiler in your current shell...

[i] INFO:
Cleaning up variables...

[root@localhost hls]# cd examples/
[root@localhost examples]# cd tutorials/hls_float/1_reduced_double/
[root@localhost 1_reduced_double]# make test
i++ -march=Arria10 part1_native_type.cpp -o part1_native_type
HLS Generate component ipxact for Platform Designer FAILED.
See /mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj/debug.log for details.
make: *** [part1_native_type] Error 1
[root@localhost 1_reduced_double]# cd part1_native_type.prj/
[root@localhost part1_native_type.prj]# cat debug.log
*******************************************************
i++ debug log file
This file contains diagnostic information. Any errors
or unexpected behavior encountered when running i++
should be reported as bugs. Thank you.
*******************************************************

Compiler Command: i++ -march=Arria10 part1_native_type.cpp -o part1_native_type

***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries. Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2020.10.18.21:58:18 Info: Doing: qsys-script --script=poly_approximate_sine.tcl --quartus-project=none
2020.10.18.21:58:22 Info: create_system poly_approximate_sine
2020.10.18.21:58:22 Info: set_project_property HIDE_FROM_IP_CATALOG false
2020.10.18.21:58:22 Info: set_project_property DEVICE_FAMILY Arria10
2020.10.18.21:58:22 Info: Info: The device and speed grade is changed to the defaults of the device family, Arria10.
2020.10.18.21:58:22 Info: set_project_property DEVICE 10AX115U1F45I1SG
2020.10.18.21:58:22 Info: add_instance poly_approximate_sine_internal_inst poly_approximate_sine_internal
2020.10.18.21:58:22 Info: set_instance_property poly_approximate_sine_internal_inst AUTO_EXPORT true
2020.10.18.21:58:22 Info: save_system poly_approximate_sine.ip
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries. Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2020.10.18.21:58:28 Info: Saving generation log to /mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj/components/poly_approximate_sine/poly_approximate_sine/poly_approximate_sine_generation.rpt
2020.10.18.21:58:28 Info: Generated by version: 20.2 build 50
2020.10.18.21:58:28 Info: Starting: Create HDL design files for synthesis
2020.10.18.21:58:28 Info: qsys-generate /mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj/components/poly_approximate_sine/poly_approximate_sine.ip --synthesis=VERILOG --output-directory=/mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj/components/poly_approximate_sine/poly_approximate_sine --family="Arria 10" --part=Unknown
2020.10.18.21:58:28 Warning: poly_approximate_sine_internal_inst: Invalid device name in input file: 10AX115U1F45I1SG
2020.10.18.21:58:28 Error: poly_approximate_sine: deviceFamily "Arria 10" is out of range: "None", "Unknown"
2020.10.18.21:58:28 Error: qsys-generate failed with exit code 3: 1 Error, 1 Warning
2020.10.18.21:58:28 Info: Finished: Create HDL design files for synthesis
2020.10.18.21:58:28 Info: Starting: IP-XACT
2020.10.18.21:58:28 Info: qsys-generate /mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj/components/poly_approximate_sine/poly_approximate_sine.ip --synthesis=VERILOG --ipxact --output-directory=/mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj/components/poly_approximate_sine/poly_approximate_sine --family="Arria 10" --part=Unknown
2020.10.18.21:58:28 Info: Finished: IP-XACT
[root@localhost part1_native_type.prj]# pwd
/mnt/data/intelFPGA_pro/20.2/hls/examples/tutorials/hls_float/1_reduced_double/part1_native_type.prj
[root@localhost part1_native_type.prj]#

Thanks a lot.

steven

 

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3 Replies
Highlighted
61 Views

Hi,

Can you run below and share the log again:

make test-x86-64

make test-fpga

 

Reference can be found below on page 16:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-start...

 

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Highlighted
Beginner
54 Views

Hi,

I run the commands you mentioned by the example counter on the directory hls/example/counter

make test-x86-64 : execution is successful

make test-fpga: same errors occurred. The debug.log is attached.

Thanks a lot.

Yiyu

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Highlighted
51 Views

Hi,

Please follow and setup thoroughly the Getting started guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-start...

Especially on page 10 where you set up the environment for the "ini_hls.sh" etc, once done, please re-do the tutorial again.

 

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