Curly braces

[Altera_Forum]

Hi, 

 I was looking through a program and found the following code  {a2, a1} <= {a1, b};  I am not sure whether the program that I'm going through is written in Verilog or System Verilog. I know the curly braces are used for concatenation operation in verilog, but then I don't quite follow what kind of concatenation is being done here. Also since I'm not sure whether the given snippet is in verilog or system verilog, I'm left confused with the code. Also does curly braces denote another operation in system verilog..?  Thanks in advance :)

[Altera_Forum]

--- Quote Start ---  Hi,  I was looking through a program and found the following code  {a2, a1} <= {a1, b};  I am not sure whether the program that I'm going through is written in Verilog or System Verilog. I know the curly braces are used for concatenation operation in verilog, but then I don't quite follow what kind of concatenation is being done here. Also since I'm not sure whether the given snippet is in verilog or system verilog, I'm left confused with the code. Also does curly braces denote another operation in system verilog..?  Thanks in advance :)  --- Quote End ---    It could be a shift operation: a2 < a1; a1 <= b;

[Altera_Forum]

--- Quote Start ---  It could be a shift operation: a2 < a1; a1 <= b;  --- Quote End ---    Thank you for the answer. Yes it is a shift. What I really wanted to know was why concatenation is being done on the right hand side. I figured that both on the LHS and RHS the given two registers are concatenated together (on each side) and then mapped bit by bit.

[Altera_Forum]

If a1, a2, b are all the same bit width, then: 

 {a2, a1} <= {a1, b};  is the same as writing:  a2 <= a1; a1 <= b;  or even:  a1 <= b; a2 <= a1;  the result will be the same given the non-blocking assignment usage. The curly brace version is just a syntactical shorthand.  However, if the bit widths of a1, a2, and b are not all the same, then other operations could be taking place. So the real answer is 'it depends'.