Custom Platform CycloneV

[Altera_Forum]

Cheers, 

 Currently I am working with Intel openCL sdk for cyclone V. I completed the getting started guide and now I am researching more in deep about the quartus project created in bin folder for compilation with aocl of the project. AOCL generates one folder a 2 files in bin folder, project.aocx, project.aoco and project<folder>. Inside project folder there is a quartus project. I read the custom platform tool guide for opencl and opencl cyclone v andthe information is not clear for me.   What means custom platform? I am understanding a custom platform as a new project to build a new electronic device. If my understanding about this information is not bad, it means that creating a custom platform is a obligatory step for build a electronic device with altera soc fpga. In my case I will use a cyclone v, so in order to save time I reuse (copy and paste) the c5soc template board. I change the name of the folder to myc5soc, and the board_spec.xml name parameter to myc5soc. I compile this and host application and then run in cyclone v dev kit board but I got a message of issue from the execution in linux in soc-fpga cyclone v:  " Context callback: Program was compiled for a different board. aocx is for board myc5soc whereas device is c5soc Use aocl program to safely transition to the new board . Context callback: Invalid binary ERROR: CL_INVALID_BINARY "  I don't understand the issue, because I just change the name and not the platform_type parameter in xml file which I guess is more critical that a simple platform name. However, I am trying to delete my5soc folder, and make a backup of c5soc to customized the c5soc template without change anything and just modify the verilog template for change the frequency of ledfpga more slowly.  Another question: What is the process to add a verilog module when the compilation step is done. I mean, if I compile a project and this generate me a aocx file, what about if i need to change something as add a extra module or just edit the verilog template (top.v) in the project and compile again. it is just possible modifying the template at the beginning of the process before compile or I can modify after and then compile just the last part for saving time.  My goals for this researching are: - Create a project written in opencl (filter and image processing) and then add a interface (in verilog languaje) to use the SDI video port of the development board. - Create a getting started guide to use opencl in cyclone v with the project mentioned.  I will be deeply thankful for your help.

[Altera_Forum]

A. Custom platform BSP, means you can have your-own platform for OpenCL. You can integrate some IO interfaces, or other FPGA IP(s) into system.  

 B. After .aocx is created , you need to run command 'aocl program /dev/acl0 this.aocx' to configure FPGA , then in host application, it need to get this.aocx content for OpenCL standard procedure to create kernel to run.  C. For your project you may need:  1) Custom you BSP, modify iface\acl_iface_system.qsys & system.qsys, board_spec.xml...   2) Write OpenCL kernel code.  3) Write host application (Linux application)

[Altera_Forum]

Thank you so much. 

 The third point, I already read the document for custom board and also see the video trainings for make a custom board. However, I find so difficult to edit the bsp c5soc to add my own io interfaces. The hard part is editing the mmd layer for driver the api opencl with the interface created. Do you have any advice? I already add my io interface to qsys project.