Cyclone V PLL issue with dynamic phase shift.

[BrianHG]

Hello, this is the first test with Cyclone V.

I've attached a small Quartus Prime 20.1 project where I configured a PLL with 'Enable access to dynamic phase shift ports' turned on.

I'm getting issues when compiling in Quartus and when doing a RTL Simulation in Altera Modelsim.  These issues are not there when I do not have that phase port enabled.

1) Quartus compile warnings:

Warning (10034): Output port "lvds_clk" at altera_pll.v(320) has no driver

Warning (10034): Output port "loaden" at altera_pll.v(321) has no driver

Warning (10034): Output port "extclk_out" at altera_pll.v(322) has no driver

Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(632) has no driver

Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(637) has no driver

Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(641) has no driver

Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(642) has no driver

Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic.

None of these ports exist in the function 'cvpll.v' which your IP generator generated.

None of these warnings exist when the dynamic phase shift ports are disabled.  How do I get rid of the warnings?

2) Altera Modelsim RTL Simulation.

In my project, my TestBench does startup and properly simulate, but, I get over three-hundred warnings in the transcript with a huge number of unconnected ports and a warning I have never seen before containing the phrase 'Missing connection for port '<protected>'.'.

Please compile my attached project and then run an RTL simulation to see what happens in the transcript.  This should not be normal as my sims use the transcript for important information.  And once again, if I disable the dynamic phase shift port, not a single warning, except I need the dynamic phase shift port.

What steps do I take to properly eliminate all those warning?

[Ash_R_Intel]

Hello,

The issue seems to be due to 'pll_type' parameter passed to the generic altera_pll component from the IP generated wrapper file cvpll_0002.v, and the assignment to lvds_clk and loaden ports in altera_pll.

For some reason, when dynamic phase shift is enabled, the pll_type = 'Cyclone V', whereas when not enabled, pll_type = 'General'.

The lvds_clk and loaden ports are applicable only for Arria 10 devices. These ports are driven by 0 when pll_type = 'General' or Arria 10 pll ports. For rest of the pll_type values, it is left undriven.

Logically it will not cause any functional issue in your design, so you can safely ignore the warnings.

Regards

[BrianHG]

Hello Ash R,

     Thank you for your reply.  Ok, the PLL does appear to simulate fine, though I do not yet have hardware to prove that.  The Quartus warnings arent too bad, however since I am providing my source code to third parties for operation and simulations, how do I explain that the 20 pages of over 300 warnings generated is a problem with Altera/Intel's code and nothing I've done wrong where as my example source for Cyclone IV/Max10 are free of such a huge list of warnings?  It covers up/buries the 5-10 pieces of important information I officially try to generate in the transcript during the simulation which verifies my design.