DDR Diff Clock Assignment Woes

[Altera_Forum]

The QII HPC Megafunction Wizard generates a HPC controller block with the differential mem_clk[1..0] and mem_clk_n[1..0] outputs for my SO-DIMM design. This causes not four but EIGHT signals because QII automatically creates the negative complent signal for each signal defined as differential. 

 How should this situation be handled? Should I not assign output pins for the mem_clk_n[1..0] outputs from my HPC block, only assign pin locations for the positive mem_clk[1..0] signals in the pin planner and let QII assign the negative pin location automatically?  Note that the complement clock signal is not automatically assigned.  Screenshots of the problem are attached.

[Altera_Forum]

The confusion is in that memclk[1..0] have been assigned a Differential SSTL IO standard. In that case the memclk[1..0](n) pins are implied and handled by Quartus. But as the HPC has both a memclk[1..0] and memclk_n[1..0] you have to change the Differential assignment into the single-ended. You can then assign locations for memclk_n[1..0], which BTW happen to be the ones previously used by the memclk[1..0](n) signals.

[Altera_Forum]

--- Quote Start ---  The confusion is in that memclk[1..0] have been assigned a Differential SSTL IO standard. In that case the memclk[1..0](n) pins are implied and handled by Quartus. But as the HPC has both a memclk[1..0] and memclk_n[1..0] you have to change the Differential assignment into the single-ended. You can then assign locations for memclk_n[1..0], which BTW happen to be the ones previously used by the memclk[1..0](n) signals.  --- Quote End ---    But if this is done, would not the timing between memclk and memclkn differ since the memclkn signals would be sourced from the internal FPGA logic and not from the IOE? I would assume it would then be up to me to (somehow) add SDC constraints to keep the timing between the two clocks synchronized?   I think this is the correct way to handle this:  I ended up keeping the megawizard-assigned differential clocks and simply not assigning the memclkn pin locations. In fact, i removed them from the pin planner and only assigned the positive parts of the clock pairs in the pin planner - the pin planner then automatically assigned the complement signal. My design niow compiles and timing analysis passed.

[Altera_Forum]

The memory clocks are generated using ALT_DDROUT blocks which actually are in the IOE (stratixII and likes) or very close to the IOE (Cyclone families). In this case the positive and the negative pins are driven by the same clock and have the same delays making it behave as nice as a differential signal. This is different however if you have specified that the memory clock pins are a direct output of the PLL, in this case the signal needs to be specified as differential (and must use the specific pins).

[Altera_Forum]

So in short, the correct solution is to set all differential DDR2 signals as SSTL 1.8 single-ended, route out all signals to pins and explicitly assign the pin locations in the pin planner? 

 Just need to verify so i don't shoot myself in the foot!

[Altera_Forum]

Assuming you are not using direct PLL outputs, yes.