DDR2 Controller

[Altera_Forum]

I am trying use the DDR2 ALTMEMPHY with about 20 DDR2 chips. The local FAE says that it is only possible to use 8 chips as that is all the GUI will allow you to select. Is there a way to use a larger number of chips or is there some other method/core for this?  

 Thanks Trampas

[Altera_Forum]

A standard DDR2 RAM design has usually more "chips" (e.g. a two bank 64 bit 1 GBit SODIMM module has 16), and it can be used with Altera DDR2 controller, utilizing ALTMEMPHY as physical driver. So if there is a limitation, it depends on the memory organisation.

[Altera_Forum]

Well I would normally connect several parts up and make the memory bus wider, but I am using a small part that can only support 8 bit data bus. I guess I might have to try a few things and see what happens, I just hate to design a board not knowing.  

 Trampas

[Altera_Forum]

So you want to have a 8 bit memory with 20 chips selects? Altera designers probably didn't expect this to be ever needed. Furthermore, you probably would have serious signal quality issues when connecting that many bidirectional dq and dqs pins to a single bus line.

[Altera_Forum]

Yeap, I know that it is not expected or planned.  

 My application does not need high speed, 60Mhz is fine but we need a lot of memory. I might be able to go back and switch to a 16bit bus. But we are really tight on pin counts.   Trampas

[Altera_Forum]

Yes, I see. 60 MHz is unusually slow, it should basically work without ALTMEMPHY timing calibration.

[Altera_Forum]

Yeap, thus I was not too worried about number of chips. Also design is small and with 16 chips the maximum distance from FPGA is only about 2.5"  

 Trampas

[Altera_Forum]

What sort of DDR2 chips are you planning to use? Are you aware that regular DDR2 chips usually have a minimum clock speed requirement (which is about 125MHz)?

[Altera_Forum]

Good point. I didn't notice, cause I never planned CLK frequencies below 200 MHz.

[Altera_Forum]

I am going to use the MT47H128M8. I did not realize the DDR2 had a minimal clock rate. I guess I need to read the datasheet a bit more.

[Altera_Forum]

Yeah, also DDR1 has a minimum clock rate of ~80MHz. Mobile DDR is the only consumer DDR with no minimum clock rate requirement, but they are more expensive.

[Altera_Forum]

what is the minimum operating frequency for ddr2 memories?

[Altera_Forum]

For the Micron memory I am using it is 125Mhz. Note it will work slower but the DLL does not lock.  

 Be forewarned though, I have been fighting to get the memory working for 4 weeks now. If you can not design the board to use Altera's DDR2 controller then you might as well give up. At 125Mhz it is almost impossible to meet timing on 8 grade speed part.   Of course I am biased and I doubt I will ever use a Altera part again. The Altera local FAE will not return my phone calls or emails for help. Thus the support from Altera has been really poor.   Trampas

[Altera_Forum]

Can you briefly report about your configuration and what problems you experienced?

[Altera_Forum]

Hi, 

 I have seen viloations in simulations if the operating frequency of ddr2 models is below 125 MHz?  regards --sampath

[Altera_Forum]

The issues I am having are how to set up the tools such that I can measure and meet timing. Basically I can simulate the behavior of my DDR2 controller against the micron model all day long and pass everything. However when I try to compile for the FPGA it will not work.  

 I have spent weeks trying to figure out cryptic warnings and such from timing tools that 2 or 3 hours with an FAE would have solved.   When I did stuff with Xilinx they would send an FAE out to sit with you for a couple of days to get up to speed on parts. Also they would respond almost immediately with answers to questions. We are going to be doing a lot more designs with FPGAs and even putting things into the "HardCopy." The good thing is that the $3k for the Altera tools was a good price to pay to find out that we should not use Altera.   Again the problem is not the FPGA, it is minor crap. For example I tried to us the ALTDQ and ALTDQS mega functions, however the the ALTDQS does not include simulation code or library thus it was worthless, and of course FAE never responded.   Also I wanted to use the Altera DDR2 controller but they hard coded the chip selects such that they have to be connected to a pin. Where due to physical limit on number of pins we had to use a 74xx138 mux to bring out chip selects for DDR2. Thus we asked the FAE if there was an IP core for the DDR2 we could purchase which would allow us to use more than 8 chips, or if we could purchase Altera's source. Of course here again no response.   Trampas

[Altera_Forum]

I forgot to mention that I could not get the signal tap to work. Thus we had to implement our own logic analyzer to debug code.  

 Again it is most likely some minor setting, but here again a few minutes with an FAE could have saved days of work...   Trampas

[Altera_Forum]

I will say that Arrow Electronics has done a good job. Their salesman there was very supportive and recommend a consultant to help. We hired consultant and was finally able to configure modelSim so it would simulate design. However many of the issue we were having was well beyond his capabilities.  

 Trampas

[Altera_Forum]

Funny Trampas, I have never had such problems with FAEs, but sounds like you just need training on Altera's stuffs, look for app notes and webcasts on the main website

[Altera_Forum]

Yeap, well I hired a consultant to provide some training and have my application working.  

 I don't think we will be using altera on future projects. Other than the forum here the support has not been good.   Trampas

[Altera_Forum]

I understand the frustation, but you know when FAEs sense that you want them to train you , they dont tend to hang around much. Again look for free app notes and webcasts on the main site .