DFF with clock enable

[Altera_Forum]

Hello everyone, 

 I was wondering, when implementing a DFF with clock enable :  library IEEE; use IEEE.STD_LOGIC_1164.all;  entity D_FF_VHDL is  port  ( clk : in std_logic; rst : in std_logic; pre : in std_logic; ce : in std_logic; d : in std_logic; q : out std_logic ) ;end entity D_FF_VHDL;  architecture Behavioral of D_FF_VHDL is begin  process (clk) is  begin  if rising_edge(clk) then  if (rst='1') then  q <= '0';  elsif (pre='1') then  q <= '1';  elsif (ce='1') then  q <= d;  end if;  end if;  end process; end architecture Behavioral;  What happens with q when ce equals to '0'? How does the FF keeps last state? Why after q<=d line shouldn't we add :  else   q<=q?  As I understand there shouldn't be any state at which q is unknown. Hence, when the clock is rising but disabled by ce='0' state of q in unknown. Please explain. Much appreciated, Boris.   Simulation Results[/B][/B]

[Altera_Forum]

--- Quote Start ---  Hello everyone,  I was wondering, when implementing a DFF with clock enable :  library IEEE; use IEEE.STD_LOGIC_1164.all;  entity D_FF_VHDL is  port  ( clk : in std_logic; rst : in std_logic; pre : in std_logic; ce : in std_logic; d : in std_logic; q : out std_logic ) ;end entity D_FF_VHDL;  architecture Behavioral of D_FF_VHDL is begin  process (clk) is  begin  if rising_edge(clk) then  if (rst='1') then  q <= '0';  elsif (pre='1') then  q <= '1';  elsif (ce='1') then  q <= d;  end if;  end if;  end process; end architecture Behavioral;  What happens with q when ce equals to '0'? How does the FF keeps last state? Why after q<=d line shouldn't we add :  else   q<=q?  As I understand there shouldn't be any state at which q is unknown. Hence, when the clock is rising but disabled by ce='0' state of q in unknown. Please explain. Much appreciated, Boris.   Simulation Results[/B][/B]  --- Quote End ---    you can add that line if you wish but it is implied that if a condition is not defined it means it saves its last value.

[Altera_Forum]

Because vhdl has memory. A signal assignment lasts until it is assigned to something else. 

 you could add the line if you wanted without problem, but technically it would make simulation go slower. But no effect on synthesised result.

[Altera_Forum]

I don't understand why the statement: "VHDL has memory" is the answer. 

Because when this design starts and rst!='1', pre!=1 or ce!=1, than q is undefined. It didn't have a value yet and now it still doesn't have a defined value. This would mean there is something undefined going to happen, right? Thats how I've understood it, since we made a mistake a few times by not always defining the output. We tought everything was right, but it wasn't working. Than we added a last else statement and it worked.

[Altera_Forum]

Undefined my and it hasn t been assigned a value yet. It wont have a value without a clock edge. If ce is 1 and q is still u after rising edge, make sure d has a value.

[Altera_Forum]

--- Quote Start ---  I don't understand why the statement: "VHDL has memory" is the answer. Because when this design starts and rst!='1', pre!=1 or ce!=1, than q is undefined. It didn't have a value yet and now it still doesn't have a defined value. This would mean there is something undefined going to happen, right? Thats how I've understood it, since we made a mistake a few times by not always defining the output. We tought everything was right, but it wasn't working. Than we added a last else statement and it worked.  --- Quote End ---    I think you're right. If first rising edge is not coming then q would be U.