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Data Result affected by using signalTap and In-system memory content editor after synthesis in Quartus

Hi everyone

I am designing a DSP for a FFT in Quartus15.1 Prime SE and using both signalTap and In-system memory content editor to debug. In my design , the FFT result is stored in a RAM, therefore using In-system memory content editor to verify the result in RAM. Since I found some small bugs in the output contents in RAM so I used signalTap to see some intermediate signal nodes.

 

Without changing the code, I found that after I enabled the signalTap, the signaltap would affects some of my original signals including the FFT results. Since the RAM contents are the FFT results and most of the were correct without using SignalTap, so I compare the results in RAM after enable SignalTap. I list out some of the effects I found i this situation in the following.

 

1.Some counters would be ended at a value which is not as designed and resulting incorrect FFT results. e.g 0~1023 counter but ended at 768 and sometimes would be stucked at this value. Most likely this is the main problems caused by SignalTap.

 

2. Some triggling signals failed to triggle in signaltap. e.g My design is to use a enable pulse signal to enable the FFT unit, sometimes signaltap would cannot be triggle by this enable signal for signal recording. In this case, In-system memory content editor would also unable to update the contents.

 

3. By adding /*synthesis noprune*/, /*synthesis keep*/ to different signals, it affects the RAM contents even those line are added in unrelated signals.

 

Now, I have no way to debug my design since using SignalTap itself would affecting my design. Can anyone please help me to solve this problem?? Thank you.

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Hi,

Have you tried to simulate your design and check whether the simulation meet your expectation?

 

Please refer to this document on simulating the IP.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fft.pdf

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