Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15323 Discussions

FFT IP Core ERROR when I simulate it with MODELSIM-ALTERA (VSIM 3033)

ICace
Beginner
245 Views

Hello,

 

I'm trying to simulate the FFT IP Core block with ModelSim-Altera.

 

I have generated the testbench with the IP parameter Editor and I'm getting this error when I run the RTL Simulation:

 

What can I do?

 

** Error: (vsim-3033) c:/intelfpga/17.1/quartus/bin64/db/ip/bloquefft/submodules/bloquefft_fft_ii_0.sv(59): Instantiation of 'asj_fft_si_se_so_bb' failed. The design unit was not found.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb/bloquefft_inst/fft_ii_0 File: c:/intelfpga/17.1/quartus/bin64/db/ip/bloquefft/submodules/bloquefft_fft_ii_0.sv

#     Searched libraries:

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/altera

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/220model

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/sgate

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/altera_mf

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/altera_lnsim

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/cyclonev

#       C:/intelFPGA/17.1/quartus/bin64/simulation/modelsim/rtl_work

#       C:/intelFPGA/17.1/quartus/bin64/simulation/modelsim/bloqueFFT

#       C:/intelFPGA/17.1/quartus/bin64/simulation/modelsim/bloqueFFT

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_clk_bfm : altera_avalon_clock_source" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_rst_bfm : altera_avalon_reset_source" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_sink_bfm : altera_conduit_bfm" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_source_bfm : altera_conduit_bfm_0002" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# Error loading design

# Error: Error loading design

#    Pausing macro execution

# MACRO ./fft_on_top_run_msim_rtl_vhdl.do PAUSED at line 17

 

0 Kudos
1 Reply
CheePin_C_Intel
Employee
196 Views

Hi,

 

As I understand it, you seems to observe some issues when trying to simulate the FFT Ip in Modelsim simulation. For your information, as I tested using FFT in Q17.0Std with A10 devices, and generated the example design from IP Parameter Editor -> Generate -> Generate Example Design. As I performed simulation with the example design, it can simulate without issue in the Modelsim - Intel FPGA Edition 10.5b. Would you mind to try with the example design to see if it works on your side as well? If it works, you may cross check with you previous simulation to see if can spot any anomaly.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

 

Reply