I have a verilog design. I am trying create several different bitstreams from it, say 3. The only difference in those bit streams will be, which pins have weak pull-ups.
I know that one way to do this is to keep 3 revisions of the design and compile each separately.
Is there a more efficient way? Is there a way to synthesize and do the placement and fitting once for the whole design and then somehow link which pins should activate their weak-pullups to create 3 different bitstreams?