Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Data in HEX File overlaps between data blocks at address 8 and address 0

VCham
New Contributor I
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I am using Quartus Prime 17.0.2

When to generate a JIC file, I am able to add an SOF file with out issue, but I get an error when doing the same for HEX. 

VCham_0-1658761022070.png

The existing forum posts on this subject refer to memory files but I have not been able to locate that in my settings menu. Any assistance would be greatly appreciat

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YuanLi_S_Intel
Employee
1,436 Views

It could be due to the issue during hex file generation. Can you please follow the user guide at link below for that?

https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-from-epcq-flash.html


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VCham
New Contributor I
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Thanks for the suggestion. It seems the issue has to do with the reset vectors. 

My issue is that my current configuration is a bit unusual. We have implemented our EPCQ controller outside of Qsys/Platform Designer because the version of Quartus we are using (17.0.2) is incompatible with the EPCQ device we have. To solve this work around we implemented a v19 EPCQ controller in our top level design rather than inside Qsys. This works but presents an issue given the Embedded User Guide. Any thoughts on how to accommodate this?

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YuanLi_S_Intel
Employee
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Sorry i dont get it. How does the reset vectors affecting with EPCQ controller in platform designer? can you please clarify? So with the EPCQ controller outside of platform designer, it works? or the another way round?


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