Debugging Current State in Simulation (VHDL/Quartus)?

[Altera_Forum]

Hey, I've implemented a moore-type finite state machine using process statements and a state variable "y" which holds the current state. 

 TYPE State_type IS (state0,state1,state2...) -- lots of other states left out Signal y: State_type;  Is there a way in simulation to debug exactly what state y is currently in, without assigning output variables to each state (I have a lot of states, and this isn't very elegant..)? Like making the states represent integers and debugging those or something?  Thanks for your help.

[Altera_Forum]

Because you declared your own state, you always know what state it is in, because you decalred it. 

 States dont map to any particular encoding until synthesis. And then you can chose the encoding via the synthesis options.

[Altera_Forum]

Yes, of course I know what the state explicitly SHOULD be according to how I designed it, but I think it would be helpful to be able to explicitly show what state I am in on the vector waveform/simulation results at every point, to troubleshoot why certain outputs don't go high, etc. 

 Do you understand what I'm asking?

[Altera_Forum]

When you say explicitly, do you mean an actual encoding rather than just the state name? like "110101" instead of "state1"? 

 Are you using quartus simululator or Modelsim?

[Altera_Forum]

I'm using the quartus simulator. What I'm saying is that just as you are able to add outputs and inputs to the waveform trace when you run a simulation, I was wondering if there's a way to create an output that outputs the current state's name or the current state; I would imagine that it might just output the current state's encoding (since quartus provides encoding even if you give state names) as an integer/bit vector.. but I'm not sure.

[Altera_Forum]

Sorry I dont know about the quartus simulator (due to be dropped in Q10 btw). In modelsim you just pick up the state signal and drop it on the wave window and watch the state change.  

 I would imagine the quartus simulator wont give you state encoding as this wont be assigned until you synthesize the design.

[Altera_Forum]

With default "one hot" encoding, you actually need to display a bit for each state, it's the same e.g. in SignalTap debugging. But I don't understand, why you create an output signal. You can simply include the internal state registers to your simulation waveform.