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Valued Contributor III
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Default Gate Value when Input is Undefined

I have a simple block diagram in Quartus II that uses an AND gate. When I run a simulation on this program, I notice that the output is true when the inputs are undefined. How can I change it so that the output is false by default? The output is for an Enable pin, and I don't want it to be true at start-up.  

 

So far, changing the "Power-Up Level" of the output or input pins in the Assignment Editor does not help.
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