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Delay in vhdl

sslo0
Beginner
‎04-21-2019 03:14 PM
868 Views

hi,

I am trying to delay an input signal by a certain time delay as follow

Capture.PNG

but the problem when i simulate the signal is always delayed by 7.946 ns even if I change the time delay in the code. Please can anyone help me

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AnandRaj_S_Intel
Employee
‎04-22-2019 03:11 AM
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Hi,

 

It should work fine, I have Checked it with modelsim. Also note that delay are not synthesizable.

 

Regards

Anand

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