I have been trying to do the 8-bit accumulator as the picture attached below but can't get the desire waveform. Can anyone help me? Below are the Verilog HDL coding I had done :
module ripple_add(a, b, s, cout);
input [7:0] a,b;
output [7:0] s;
output cout;
wire c1, c2, c3, c4, c5, c6, c7;
fulladd fa0(a[0], b[0], 0, s[0], c1);
fulladd fa1(a[1], b[1], c1, s[1], c2);
fulladd fa2(a[2], b[2], c2, s[2], c3);
fulladd fa3(a[3], b[3], c3, s[3], c4);
fulladd fa4(a[4], b[4], c4, s[4], c5);
fulladd fa5(a[5], b[5], c5, s[5], c6);
fulladd fa6(a[6], b[6], c6, s[6], c7);
fulladd fa7(a[7], b[7], c7, s[7], cout);
endmodule
module acc (a, sum ,overflow, clk, carry);
input [7:0] a;
input clk;
output reg overflow;
output wire carry;
output wire [7:0] sum;
reg d1,d2,b;
reg [7:0]r1,r2;
ripple_add add(.a(a),.b(r2));
assign {carry,sum} = a+r2;
always @(posedge clk)
begin
if (sum==a)
overflow = 0;
else
overflow =1;
end
always@(posedge clk )
begin
r1=a;
r2=sum;
d1<=overflow;
d2<=carry;
end
endmodule
Thanks a lot if anyone willing to help me on this.
