Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Design using ALTERA schematic issue

Altera_Forum
Honored Contributor II
1,094 Views

As attached file shows, SQ[127] => TC[0]?

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
415 Views

 

--- Quote Start ---  

As attached file shows, SQ[127] => TC[0]? 

--- Quote End ---  

 

 

Yes. The "RTL Viewer" is your friend here.
0 Kudos
Reply