Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Development board outputs clock signal

xiaobai1
Beginner
238 Views

I have encountered some problems in the process of learning. I sincerely hope you can spare time to guide me.

  1. Objective: To obtain 50MHz clock signal by using CycloneV (5CGTFD9E5F35) to output onboard crystal oscillator through phase-locked loop.
  2. Problems encountered at present: the phase-locked loop was called, pins were allocated and burned into the development board, but the crystal clock signal could not be obtained.
  3. General process:

(1) Input pin information found in the manual:

xiaobai1_0-1655972124876.png

 

xiaobai1_1-1655972124891.png

 

 

 

 

(2) Output pin:

xiaobai1_2-1655972124896.png

 

xiaobai1_3-1655972124909.png

 

Output position of the corresponding development board:

xiaobai1_4-1655972124936.jpeg

 

 

(3) RTL view and pin allocation

xiaobai1_5-1655972124938.png

 

xiaobai1_6-1655972124971.png

 

(4) After the program is burned into the development board, the output is connected to the oscilloscope, and the signal can not be obtained.

xiaobai1_7-1655972125008.jpeg

 

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sstrell
Honored Contributor III
218 Views

Assuming this is the board you are using (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html), J4 connects to U3, not the FPGA.

Screen Shot 2022-06-24 at 3.47.40 PM.png

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FvM
Valued Contributor II
204 Views

Hello
according to the photo, the OP is connecting J14 (SMA_OUT) to the oscilloscope, it is in fact driven by FPGA pin AF33. Not sure why the configuration doesn't work.

Frank

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Ash_R_Intel
Employee
191 Views

Hi,

The input clock of 50MHz should be taken from V28 pin of FPGA and connect to sys_clk of your pll instance. IO standard should be 1.5V CMOS.


Regards


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