I posted a post in the community before, thank you very much for your reply.
After your reply to the author, the author also made further attempts on the development board, but the effect is still not ideal. The author sincerely asks you for advice. At present, the author wants to use the development board to generate a 50MHz clock pulse with a higher frequency.
In order to help you find out the problems and give pertinent suggestions, the author shows the general process of the experiment as follows.
- The author disassembled the LCD display on the development board and wanted to use the LCD pin as the output position of the PLL, as shown in Figure 1
Figure 1. LCD pin diagram of development board
- Call the IP core of the PLL, and burn it into the development board after successful compilation. Figure 2 shows the interface of invoking the PLL, and Figure 3 shows the result of the attempt.
Figure 2. IP core diagram of invoking PLL
Figure 3. Experimental test results
- Refer to the Cyclone V (5CGTFD9E5F35) instruction of the development board. Figure 4 shows the description of LCD pins
Figure 4. LCD pin information
- The result obtained is quite different from the expected. The oscilloscope only measured 27MHz signal, but the author set 50MHz, 25MHz and 10MHz at the output end of the PLL. Theoretically it should be possible to get three different frequency clock signals from the development board.
Can you share your design, we need to confirm the clock out pin. So that every changes you made to the pll output will take effect. Currently, the only output frequency coming out from the clock out pin is 27MHzy. I am afraid the location is different.
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