Differential CLK input handle

[kikoss]

Hello 

I have a a differential clk come in to FPGA agilex7 F series 

Want to use it as a single clk to the design 

Iam using quartus 24 .1 pro

Which good practice is recommended ?  

i see on a design a use of ALTDDIO_IN primitive . is this recomended  ? is it still relevant for quartus 24 ? 

Thx

Kikoss

[AqidAyman_Intel]

Hello,

May I know what did you need to use a single ended clock in your design instead of differential clock?

[kikoss]

Hi 

To be clearer , what i meant, is that i have a differential clk that comes into the fpga , from an adc converter 

I want to use this clock for the ALT_LVDS ip , and this IP is able to receive only single ended clk  as we see here

How to handle that in quartus ? 

Thx

[FvM]

Hi,
input and output ports of design modules and top level interface always appear as single ended signal, except for rarely used special differential IO low-level primitives. You make the port a differential in- or output by assigning a differential IO standard (e.g. LVDS) in pin planner or assignment editor to it.

[kikoss]

Yes but suppose ,  I have on TOP level , clkin_p , clkin_n  , and suppose i assign them to external pins 

What to connect to inclock  port of the adc contoller ? 

Thx 

[FvM]

Why are you using separate clkin_p and clkin_n pins in the port definition? The usual way is to have a single ended logical port and assign a differential pin pair. You can use an ALT_INBUF_DIFF low level primitive to do the translation but it has no benefit for standard differential inputs.

[kikoss]

i will explain why using separate ports

i have an ADC convertere that send data to the FPGA 

it interface from the ADC to the FPGA is . clk , and data as on the image

As you see the DCO CLK that go the FPGA is a differential pair .

So how to handle this differential pair on FPGA ? The ALT_INBUF_DIFF primitive is supported only for Stratix® III and Cyclone® III devices . and Iam not using those devices 

THX

[FvM]

Hi,
I know how an ADC LDVS interface looks like, I'm working with it since 15 years or so. Here's an example how I configure clock and data interface for AD9222, in this case I'm using FCO rather than DCO and a PLL to generate bit clock.

top entity port definition

   ADC_CLK     : OUT STD_LOGIC;

   ADC_FCO    :  IN STD_LOGIC;

   ADC_LVD     : IN STD_LOGIC_VECTOR(1 TO 8);

assigned IO standards
  set_instance_assignment -name IO_STANDARD LVDS -to ADC_LVD*
  set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
  set_instance_assignment -name IO_STANDARD LVDS -to ADC_LCLK

If you review Intel documents, you'll realize that this is the suggested way to implement differential in- and outputs.

[FvM]

Forgot to mention that single-ended port signal is assigned to positive pin of the differential pair, corresponding negative pin is assigned by fitter automatically.

[kikoss]

Hello 

OK if i understand you correctly

• you declare 1 port CLK on top level  RTL module - let say FCO_CLK  (even if its differential from the ADC)
• use this port on the RTL , for PLL input etc.. 
• assign FCO_CLK   only to  P leg on assignment editor (and not assigning at all N leg) 
• let the fitter do the job for N leg

Thats rigth ? 

THX 

[FvM · Accepted solution]

Hi,
yes. Same procedure for other differential in- and outputs.

[kikoss]

Yes , in the example i provide , I agree that this procedure should be applied to the FCO CLK  or for the DCO CLK's that are connected to the inclock port (see figure)

But , for the rx_in_p and rx_in_n,  the ALT LVDS ip called adc_controller (in the figure above) handle differential P and N legs ... so I understand that we must declare P and N as well on the RTL as separate ports . rigth ? 

THX

[AqidAyman_Intel]

Hi,

I wish to follow up with you. Did your issue is resolved after following the suggestion by @FvM?

Regards,

Aqid

[kikoss]

Hello Yes its ok 

THX

[AqidAyman_Intel]

Hello,

Thank you for your confirmation. I’m glad that the issue has been addressed. If you have a new question and new more support, feel free to log in to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.