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Novice
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Do ROM and/or Lookup Tables introduce an additional delay to the overall circuit?

I want to design a circuit in which a 5-bit input In[4:0] (ranges from 0 to 31) is associated with a corresponding 3-bit output Out[2:0]. I can design this using a 8x3 Encoder in which 5 out of 8 inputs can be connected to In[4:0] to provide the corresponding output, and other inputs (3 out of 8 inputs of encoder) can be set to 0. However, using an encoder will introduce an additional delay.

I can also use a lookup table (LUT) which has 32 locations. The 5-bit input In[4:0] can be used as the address for LUT and the storage size of LUT will be 3 bit to store the output Out[2:0]. The 3-bit output value can be stored in the LUT corresponding to the a given input.

 

My understanding is:

If we use a lookup table and store the data, the data will be available as soon as we provide the clock signal and it  won't require additional delay like encoder.

 

Please suggest me whether to use an encoder or LUT if the main aim of the design is to reduce the processing time.

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Moderator
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Hello PSriv8,

 

Thank you for contacting Intel® Memory & Storage Support.

 

To help you to get the proper support, and an answer to your inquiry, we will appreciate it if you can let us know the Intel® product that you need support for.

This because your case reached the Intel® Software Storage Technologies forum, and it does not seem to be related to an Intel® SSD or an Intel® RAID solution.

 

We will be looking forward to your reply.

 

Best regards.

 

Josh B.

Intel® Customer Support Technician

A Contingent Worker at Intel®  

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Novice
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Hi,

 

I am sorry but I think I have selected the wrong forum mistakenly. I am working on Cyclone IV FPGA and using Quartus software. Do I need to post my question again in FPGA forum?

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Moderator
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Hello PSriv8,

 

Thank you for your reply.

 

Let me help you to move it to the proper forum, and to select the appropriate product.

 

My partners will be answering as soon as possible.

 

Thank you for your patience and understanding.

 

Best regards.

 

Josh B.

Intel® Customer Support Technician

A Contingent Worker at Intel®  

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Hi,

 

Where do you implement the encoder, is it in the core logic? Do you register the data?

 

Thanks.

Best regards,

KhaiY

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Novice
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Hi,

 

I am designing the encoder in Quartus software as a part of asynchronous digital circuit. What do you mean by registering the data?

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Hi,

I am sorry for the confusion. I meant adding a register to the output of the data -- synchronous. For Asynchronous and synchrnous circuit, both use the LUT. For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM.  The ALM can drive out registered and unregistered versions of the LUT or adder output depending on your design.

 

Thanks.

Best regards,

KhaiY

 

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Novice
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Hi,

Thank you for your reply.

I am using an asynchronous design which needs a Request signal to start a process and Acknowledge Signal is sent once the process is complete, unlike synchronous circuits where clock signal(s) exists to coordinate their activities.

Now if I store the 3-bit data in LUT, where LUT is used as memory.. and I send a Request signal to start the process, would it take additional time to access the data from memory? As I mentioned before, I can also use an 8x3 encoder in place of memory to provide the 3-bit output. Do the memory and encoder both take the same amount of time to process the data once the Request signal is available ?

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Hi,

 

Where do you implement the 8x3 encoder? Is it in the core logic? Are you using any Intel FPGA IP? If it is in the core logic, the 8x3 encoder is using the LUT as well.

 

Thanks.

Best regards,

KhaiY

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Novice
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Hi,

 

I am using only simulation to design my circuit, and I have written a code in Verilog for 8x3 encoder. I am not using existing 8x3 encoder in Intel FPGA.

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Hi,

 

You may locate the encoder module in the Chip Planner and see where is it located.

 

Thanks.

Best regards,

KhaiY

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Highlighted
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Hi,

 

Do you have any updates? Can you see where the 8x3 encoder located in the Chip Planner?

 

Thanks.

Best regards,

KhaiY

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Novice
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Hi,

 

Thank you for replying me. I do not have the whole design yet, I am still writing codes for other modules for my design. Therefore I could not use the chip planner. However, I understood that whether I will be using the LUT as memory or as encoder, both will introduce delay in the circuit. Thank you for all your replies.

 

Warm Regards

Pallavi Srivastava

 

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Hi,

 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Best regards,

KhaiY

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