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Hi all,
iam trying to run a test bench on the ip 'altddio_in', here i have used 8bit altddio_in ip
for the input data (data is available in both rising and falling edges), we are supposed to get rising edge data in 'data_out_h' and falling edge data in 'data_out_l', but iam getting same data as output for both falling and rising edge. Please see the attached image for a better idea. Thanks in advance for anyone willing to take a look.
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Can you provide the testbench and design code? No way to tell what's going on here without seeing the design.
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Is it possible to attach the snippet of your tb?
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Noted. Let me know if there is any other concern on this.
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