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avk
New Contributor I
238 Views

Elaboration of entities that are generated take very long time

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Hi all,

I have a design where I generate a large number (496) of enities. They are note very big in logic, around 13 ALM's in a CycloneV SOC. My problem is, that the elaboration step for these entities takes roughly 13 minutes which is about the same time that I need to fit the complete design, which is much bigger than just these generated entities. Is there something I can do to speed up the elaboration of these entities ?

I already tried to define a design partition with post synthesis netlist, but the elaboration step is still processed.

 

BR Andreas

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avk
New Contributor I
157 Views

So I had the opportunity to move our build machine to a Intel Proessor machine which makes my synthesis step roughly 50% faster, the fitter step not 50% but still remarkably faster. If you guys stumble over this post with the same issue, please drop a line in this thread in order to show Intel this is an issue.
I will however stop investigation here since I am happy with this workaround.
@KhaiChein_Y_Intel I am not allowed to share this design since it is under NDA Agreement sorry.

View solution in original post

11 Replies
sstrell
Honored Contributor II
233 Views

Can you post any code?  That might help to figure out what's taking so long just for elaboration, which is normally pretty quick.

#iwork4intel

avk
New Contributor I
228 Views

This is the part that generates all the entities, ADDR_ARRAY and ACT_READ_ACCESS_IND_ARRAY are both arrays that define the configuration of the entities. ASYNC_IN_PORT_MAPPING and ASYNC_OUT_PORT_MAPPING are Arrays containing the signals that can be read or written by accessing the respective adresses. The whole thing basically defines a adressable registerbank. I know it could be done with a Dualport RAM, but for now we have this solution and need to speed the build process up.

  ASYNC_GEN:
  for i in 0 to (NBR_ASYNC_PORTS-1) generate
    async : entity work.IF_ASYNC_PORT_V2 
      generic map(
        ADDR => ADDR_ARRAY(i),
        ACT_READ_ACCESS_IND => ACT_READ_ACCESS_IND_ARRAY(i))
      port map(
        nRESET                => nRESET, 
        CLK                   => CLK, 
        CTRL                  => s_ctrl_clk, 
        DATA_IN               => s_em1d_in_clk,
        DATA_OUT              => EM1D, 
        nOE                   => nEM1OE,
        DATA_FPGA_TO_DSP      => ASYNC_IN_PORT_MAPPING(i), 
        DATA_DSP_TO_FPGA      => ASYNC_OUT_PORT_MAPPING(i),
        READ_ACCESS_INDICATOR => ASYNC_OUT_READ_ACC_INDICATOR(i)
        );
  end generate ASYNC_GEN;

 

sstrell
Honored Contributor II
209 Views

The only thing that seems odd is the way you're referencing the entity you want to instantiate each loop:

async : entity work.IF_ASYNC_PORT_V2

 I don't know if maybe Quartus is searching the whole work directory (the project directory) each iteration of the loop to try to find this and that is what is slowing things down.  If the file that contains this entity is already in the project directory (or referenced using an IP search path in Quartus settings), then maybe try just:

async: IF_ASYNC_PORT_v2

Or perhaps you need LIBRARY and USE clauses at the top of this design file to point to this.

Some things to try.

#iwork4intel

 

avk
New Contributor I
197 Views

Hi,

Thanks for your reply. I tried to move the component into a package and made it available with a "use". Although it makes the project tydier, it did not help to speed up things. I however suspect now something else to cause this: I think, the big Arrays that are used to assign the signals to this component slow everything down. Will try with a smaller batch of entities first to see if this makes it faster. Keep you posted...

189 Views

Hi,


May I know if you have any updates?


Thanks.

Best regards,

KhaiY


avk
New Contributor I
186 Views

Hi KhaiY

Yes and No... I haven't yet finished the tests with smaller arrays, so no I have no updates for the Moment regarding this. But I have interesting information from another end: I moved to another physical machine that is meant to be slower regarding the technical spec's. Surprisingly it is more than two times faster for this entity elaboration and about 1.5 times faster in the fitter step. I know I am not allowed to share detailed benchmark data (for whatever reason), but the VERY interessting fact is, that the Processor which takes so much longer in elaboration step is a Product from an Intel competitor. There are other messages in this forum and on other sites in the internet reporting the same observations. It would indeed be interesting to have an official statement from Intel regarding these difference.

Also i discovered, that turning off hyperthreading makes Quartus faster... Another fact where it might be interesting to have official information from Intel.

Best regards

179 Views

Hi,


I found three KDB about the compilation time. You may try the suggestions in the KDB below.

  1. What PC should I buy to get the fastest compilation time for the Quartus II software?https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...
  2. Why don't I see the expected compilation time reduction with parallel compilation?https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...
  3. How can I improve the compilation time performance of the parallel compilation feature in the Quartus II software?https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

Thanks.

Best regards,

KhaiY


avk
New Contributor I
174 Views

Hello,

Thanks for pointing to these links. I tried all of them before and they did not help. I didn't expect a lot from them beforehand since they are greatly outdated anyway... Waiting for more helpful stuff from you Intel guys.

BR

161 Views

Hi,


You may share the design.qar for me to try to compile here. To generate the design.qar, click on Project > Archive Project > Archive.


Thanks.

Best regards,

KhaiY


avk
New Contributor I
158 Views

So I had the opportunity to move our build machine to a Intel Proessor machine which makes my synthesis step roughly 50% faster, the fitter step not 50% but still remarkably faster. If you guys stumble over this post with the same issue, please drop a line in this thread in order to show Intel this is an issue.
I will however stop investigation here since I am happy with this workaround.
@KhaiChein_Y_Intel I am not allowed to share this design since it is under NDA Agreement sorry.

View solution in original post

142 Views

Hi,


Sure. Since you have found a workaround by changing another machine to run on, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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