Hi All,
In my design I need a pll to generate two synchronous clocks therefore
I generated a pll using MagaWizard tool. I selected Enhanced PLL option for pll type. Input clock frequency of the pll is set to 19.2Mhz and C0 and C1 outputs are set to 20Mhz and 52Mhz respectively. Most of the other parameters are set as their default values. One of the outputs of the pll is used as main clock of the design. I used a clkctrl module to multiplex the pll outputs.
The problem which I had is that when I compile my design I get the following warning message;
Warning: PLL "pll_main:i_pll_main|altpll:altpll_component|pll" has settings that may result in high compensation variabilit
Warning: PLL "pll_main:i_pll_main|altpll:altpll_component|pll" has settings that may cause the lock circuit to fail due to high compensation variability
I tried to eliminate this warning by changing a few seetings of the pll but I could not achive to remove it.
I would be very thankful if anybody can help me.
Thanks in advance
Ihtopcu
Stratix II EP2S60F1020C3
Quartus II Version 8.0, service Pack Installed: 1
