Error 10500

[Altera_Forum]

Hi, i have problems with my vhdl code.  

This is the code: LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;   ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;   ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;   BEGIN   readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);   registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  D <= (others =>'0');  v <= (others =>'0');  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  D (31 downto 0) <= unsigned(writedata (31 downto 0));  else v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  end if; END PROCESS;   distance : PROCESS (clk,reset) begin  if reset = '0' then  D <= (others =>'0');  elsif clk'event and clk='1' then   D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  else  D <= (others =>'0');  end if; END PROCESS;   tableau_de_bord : PROCESS (clk,reset)  begin  if reset = '0' then  tb <= '0';  elsif clk'event and clk='1' then  tb <= '0' when D < Dmax else   '1' when D > Dmax;  end if; end process;   frein : PROCESS (clk,reset) begin  if reset = '0' then  brake <= '0';  elsif clk'event and clk='1' then  brake <= '0' when tb = '0' else   '1' when tb ='1';-- freinage  end if; END PROCESS;   out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;  And the error : Error (10500): VHDL syntax error at ppp.vhd(61) near text "when"; expecting ";" Error (10500): VHDL syntax error at ppp.vhd(71) near text "when"; expecting ";" Error: Quartus II 32-bit Analyze Current File was unsuccessful. 2 errors, 0 warnings  Error: Peak virtual memory: 329 megabytes  Error: Processing ended: Sun May 25 19:34:03 2014  Error: Elapsed time: 00:00:03  Error: Total CPU time (on all processors): 00:00:03  Help me please it's urgent.

[Altera_Forum]

you are mixing up between combinatorial conditional syntax and process based one. 

do not use when inside the process.

[Altera_Forum]

i could you plz be more specific ?  

i used if instead of when but i got this error : Can't infer register for because it does not hold its value outside the clock edge  Error (10818): Can't infer register for "D[0]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[1]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[2]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[3]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[4]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[5]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[6]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[7]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[8]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[9]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[10]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[11]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[12]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[13]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[14]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[15]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[16]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[17]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[18]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (12152): Can't elaborate user hierarchy "projetppp:inst|brake_var:ppp_inst" Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 20 errors, 7 warnings  Error: Peak virtual memory: 371 megabytes  Error: Processing ended: Sun May 25 19:59:59 2014  Error: Elapsed time: 00:00:10  Error: Total CPU time (on all processors): 00:00:10 Error (293001): Quartus II Full Compilation was unsuccessful. 22 errors, 7 warnings

[Altera_Forum]

you have many other errors e.g. multiple drive on D. 

you have to be careful as I don't think your brake system will brake

[Altera_Forum]

do you have some advices ? 

because i'm a little bit lost :/ :/  and thank you very much :)

[Altera_Forum]

Error (10818): Can't infer register for "D[0]" at ppp.vhd(47) because it does not hold its value outside the clock edge 

Error (10818): Can't infer register for "D[1]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[2]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[3]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[4]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[5]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[6]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[7]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[8]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[9]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[10]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[11]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[12]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[13]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[14]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[15]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[16]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[17]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[18]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (12152): Can't elaborate user hierarchy "projetppp:inst|brake_var:ppp_inst" Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 20 errors, 6 warnings  Error: Peak virtual memory: 371 megabytes  Error: Processing ended: Sun May 25 20:16:52 2014  Error: Elapsed time: 00:00:14  Error: Total CPU time (on all processors): 00:00:12 Error (293001): Quartus II Full Compilation was unsuccessful. 22 errors, 6 warnings  here is what i got when i changed the code like this :   LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  D <= (others =>'0');  v <= (others =>'0');  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  D (31 downto 0) <= unsigned(writedata (31 downto 0));  else v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  end if; END PROCESS;  distance : PROCESS (clk,reset) begin  if reset = '0' then  D <= (others =>'0');  elsif clk'event and clk='1' then   D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  else  D <= (others =>'0');  end if; END PROCESS;  tableau_de_bord : PROCESS (clk,reset)  begin  if reset = '0' then  tb <= '0';  elsif clk'event and clk='1' then  if  D < Dmax then tb <= '0' ;  else   tb <='1' ;  end if ;  end if; end process;  frein : PROCESS (clk,reset) begin  if reset = '0' then  brake <= '0';  elsif clk'event and clk='1' then  if tb = '0'   then brake <= '0';  else brake <='1'; -- freinage  end if;  end if; END PROCESS;  out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

[Altera_Forum]

LIBRARY IEEE; 

use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  D <= (others =>'0');  v <= (others =>'0');  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  D (31 downto 0) <= unsigned(writedata (31 downto 0));  else v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  end if; END PROCESS;  distance : PROCESS (clk,reset) begin  if reset = '0' then  D <= (others =>'0');  elsif clk'event and clk='1' then   D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  else  D <= (others =>'0');  end if; END PROCESS;  tableau_de_bord : PROCESS (clk,reset)  begin  if reset = '0' then  tb <= '0';  elsif clk'event and clk='1' then  if  D < Dmax then tb <= '0' ;  else   tb <='1' ;  end if ;  end if; end process;  frein : PROCESS (clk,reset) begin  if reset = '0' then  brake <= '0';  elsif clk'event and clk='1' then  if tb = '0'   then brake <= '0';  else brake <='1'; -- freinage  end if;  end if; END PROCESS;  out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

[Altera_Forum]

instead of 

tableau_de_bord : PROCESS (clk,reset) begin if reset = '0' then tb <= '0'; elsif clk'event and clk='1' then tb <= '0' when D < Dmax else '1' when D > Dmax; end if; end process;   something like this below:  tableau_de_bord : PROCESS (clk,reset) begin if reset = '0' then tb <= '0'; elsif clk'event and clk='1' then if D < Dmax then tb <= '0'; elsif D > Dmax then tb <= '1'; end if; end if; end process;   and the same for other process

[Altera_Forum]

i did that but i got 22 errors like this one :Error (10818): Can't infer register for "D[0]" at ppp.vhd(47) because it does not hold its value outside the clock edge  

do you have any idea what should i change next ?

[Altera_Forum]

D is wrong all over. It is assigned in two processes. You need to make your mind what should D be. 

also note you should not use else for the if of clock edge as it is not meant to be combinatorial.

[Altera_Forum]

D is a breaking distance with D formula is D = (v(means speed) x3 )/10 + v²/100  

and i didn't understood => "you should not use else for the if of clock edge as it is not meant to be combinatorial."  thank you very much

[Altera_Forum]

In that case assign to D what you are after in one process only as below. Later you need to sort out your divisions. 

 comment out as below   distance : PROCESS (clk,reset) begin if reset = '0' then D <= (others =>'0'); elsif clk'event and clk='1' then D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; --else --D <= (others =>'0'); end if; END PROCESS;

[Altera_Forum]

i got this  

Error (10028): Can't resolve multiple constant drivers for net "D[31]" at ppp.vhd(47) and many similars errors :p   (sorry for that amount of question but i need to fix it for tomorrow :( :( : ( ) thank you very much

[Altera_Forum]

I already told you that D must be assigned in one process only. So the assignment in first process means two drivers(you can't drive a bus with two drivers!). 

If you want D to have different assignments then include all that in set of statements inside one process.

[Altera_Forum]

so do you have any suggestion how i should change that ? 

i will be very greatfull :p :)

[Altera_Forum]

You will need to tell us what your design is meant to do before diving in any coding. Reverse engineering is painfully hard let alone if code is wrong

[Altera_Forum]

co design of and anti collision system made for cars ;  

with D the distance between the object and Dmax is the max tolerable distance  v is the car's speed  tb is an indicator that indicate is yes or no there is and object  and brake is for the abs   LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  D <= (others =>'0');  v <= (others =>'0');  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  D (31 downto 0) <= unsigned(writedata (31 downto 0));  else v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  end if; END PROCESS;  distance : PROCESS (clk,reset) begin if reset = '0' then  D <= (others =>'0');  tb <= '0';  brake <= '0'; elsif clk'event and clk='1' then  D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; --else  --D <= (others =>'0');  if D > Dmax then  tb <= '0';  elsif D < Dmax then  tb <= '1';  end if;  if tb = '0' then  brake <= '0';  elsif tb = '1' then  brake <= '1';   end if; end if; END PROCESS;  out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;  i putted it all in the same process but i got the same errors :/ :/ i'm more and more confused

[Altera_Forum]

For now D is the problem. D is the distance and according to your code you are getting it from writedata. 

but in second process you are calculating it. So which one is right?

[Altera_Forum]

i thought that i would take v from writedata and calculate then D no ?  

LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  D <= (others =>'0');  v <= (others =>'0');  tb <= '0';  brake <= '0';  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  --D (31 downto 0) <= unsigned(writedata (31 downto 0));  v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  if D > Dmax then  tb <= '0';  elsif D < Dmax then  tb <= '1';  end if;  if tb = '0' then  brake <= '0';  elsif tb = '1' then  brake <= '1';   end if;  end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;  gave me no errors but 94 warnings :D

[Altera_Forum]

you still got D assigned at reset in first process????

[Altera_Forum]

now you confused me. It is one process. May be it is better. 

can you put tags on code i.e. type [{code}] your code [{/code}] but without the curly brackets.