This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest available version for the cyclone 5).
Will it be supported soon?
Otherwhise I have to go back to synplify,
I don't want to change many RTL code files anymore by adding name to please Quartus (like I did in a previous project).
for (j=0;j<DATA_LEARN_PHASE_NUM;j=j+1) begin
mux2_clock_wrapper u_mux2_dqs_phase (
.Z ( out[j] ),
.S0 ( i_ipt_global_scan_mode ),
.D0 ( phase[j] ),
.D1 ( i_test_clk_sfck )
)/* synthesis syn_preserve=1 */;
The Quartus standard use a different synthesis engine or parser so I doubt that this will be supported in future.
You may workaround this error by adding a line as below
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
Pro was added as an offshoot from Standard specifically to support new high end devices after Altera was acquired by Intel.
Remember that Cyclone V is about 10 years old at this point, so it predates Pro's existence. There's very little incentive for adding support for such an old device in Pro.
In the past there was a Quartus II software subscription edition and a free edition.
I think the Quartus II software subscription edition was supporting the Cyclone 5, but I'm not sure anymore.
Anyway, so be it.
I guess the cyclone 10 is also not supported in Quartus prime pro, is it?
I'm able to duplicate the error when I copied code to Quartus prime 21.1 std. I have no issue when using generate in Quartus Pro 21.4. I'll check again with the internal engineer and get back to you as soon as possible.