Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

[AEsqu]

Hello,

Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest available version for the cyclone 5).

Will it be supported soon?

Otherwhise I have to go back to synplify,

I don't want to change many RTL code files anymore by adding name to please Quartus (like I did in a previous project).

Code example:

genvar j;
generate
for (j=0;j<DATA_LEARN_PHASE_NUM;j=j+1) begin
mux2_clock_wrapper u_mux2_dqs_phase (
.Z ( out[j] ),
.S0 ( i_ipt_global_scan_mode ),
.D0 ( phase[j] ),
.D1 ( i_test_clk_sfck )
)/* synthesis syn_preserve=1 */;
end
endgenerate

[YEan]

Hi,

Do you mind to share you design .qar for me to duplicate the error?

Thanks,

Ean

[AEsqu]

Hi Ean,

The RTL code construction is above, you can add it in any verilog file.

I will not share design file nor .qar.

[AEsqu]

Just use generate without name.

[YEan]

Hi,

I have try to recreate the project but I can't duplicate the error. I have attached my design below, could you please modified the design?

Thank you.

Best regards,

Ean

[AEsqu]

Hello,

The qar seems corrupted.

I use Quartus prime 21.1 std (latest supporting the Cyclone 5).

See the attached picture for the error.

[YEan]

Hi there,

Quartus Pro and Quartus standard use different front end code base. Unfortunately, we have no plan to change Quartus Standard front end currently.

Thanks,

Ean

[AEsqu]

I will use Synplify for now then.

Please inform us when Quartus STD properly compiles the verilog.

Alex.

[RichardTanSY_Intel]

Hi @AEsqu 

The Quartus standard use a different synthesis engine or parser so I doubt that this will be supported in future. 

You may workaround this error by adding a line as below

for (j=0;j<DATA_LEARN_PHASE_NUM;j=j+1)

begin: a_name

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[AEsqu]

Hi Richard,

I don't understand why the quartus pro edition does not support the Cyclone (V) FPGA's.

That would solve this issue (we have pro licenses).

Alex.

[sstrell]

Cyclone V is only supported in Standard (and Lite which is free).  If that's the device you're targeting, you should have a Standard license, not Pro.  Pro only supports high end devices: Arria 10, Cyclone 10 GX, Stratix 10, and Agilex.

[AEsqu]

Yes I know that,

but I don't understand why using that strategy.

Why not adding the Cyclone FPGA in the better pro version?

[sstrell]

Pro was added as an offshoot from Standard specifically to support new high end devices after Altera was acquired by Intel.

Remember that Cyclone V is about 10 years old at this point, so it predates Pro's existence.  There's very little incentive for adding support for such an old device in Pro.

[AEsqu]

Hi,

In the past there was a Quartus II software subscription edition and a free edition.

I think the Quartus II software subscription edition was supporting the Cyclone 5, but I'm not sure anymore.

Anyway, so be it.

I guess the cyclone 10 is also not supported in Quartus prime pro, is it?

[sstrell]

The old Altera subscription edition is now Standard and the free web edition is now Lite. Cyclone 10 GX is supported in Pro while Cyclone 10 LP is supported in Lite and Standard.

[AEsqu]

Than you for the explanation.

I propose to close the ticket as there will be no change for the Cyclone 5.

[YEan]

I'm able to duplicate the error when I copied code to Quartus prime 21.1 std. I have no issue when using generate in Quartus Pro 21.4. I'll check again with the internal engineer and get back to you as soon as possible.

Thanks,

Ean