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It seems this issue may not have been resolved, at least not in a way that applies to SystemVerilog `interface` objects.
This is a toy example, but I can provide Quartus project upon request. I am using 23.1.1std.
The following code, given a defined interface with a parameter DATA_WIDTH_BYTES...
module foo (
input logic clk,
input logic arstn,
axis.s s_axis,
axis.m m_axis
);
localparam DATA_WIDTH = s_axis.DATA_WIDTH_BYTES * 8;
...
endmodule
...will produce the following error:
Error (10742): Verilog HDL error at foo.sv(7): constant expression cannot contain a hierarchical identifier
This doesn't seem to violate any SystemVerilog language standards; indeed Verilator and Vivado synthesize the design without complaint.
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Hi,
I hope you're doing well. May I know if the issue has been resolved, or if you still require assistance with this case?
Best regards,
Richard Tan
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Hi,
Do you need any further assistance from my side?
Regards,
Richard Tan
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Could you share a simplified project that could duplicate the error?
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.
Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.
Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.
Regards,
Richard Tan
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That is completely understandable. I do have a major demonstration tomorrow, so I will likely have to use the weekend to create a simple project that demonstrates the issue. It shouldn't take me longer than an hour or so. Thanks for your patience!
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Noted. Wishing you all the best for your upcoming demo!
Regards,
Richard Tan
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Hi,
Do you able to share the project?
Regards,
Richard Tan
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I have attached a Quartus archive of an example project. You should be able to see it creates the error message:
Error (10742): Verilog HDL error at axis_thrower.sv(6): constant expression cannot contain a hierarchical identifier
This should not be the case. With both Vivado and Verilator, the expression is allowed because their compilers deduce what is obviously constant at compile-time. Without support for this feature, interfaces are largely useless as their associated metadata has to be passed via separate channels regardless.
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Unfortunately, modport interfaces are not supported in Quartus Standard. Consequently, any struct (SystemVerilog) used in a port list must have all members defined as either in or out directions.
Additionally, Quartus Prime Standard Edition has limited support for SystemVerilog.
If the same design is compiled in Quartus Pro, it should compile successfully.
Regards,
Richard Tan
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Dropping a note to ask if my last reply was helpful to you.
Do you need any further assistance from my side?
Regards,
Richard Tan
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We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.
If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you for reaching out to us!
Best Regards,
Richard Tan
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