Error (11802): Can't fit design in device. Modify your design to reduce resources,

[Altera_Forum]

I have successfully run vector_add on the de0nano board example, but when i run the example of matrix_mult, I encountered the above error and view the log as follows: 

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Info (144001): Generated suppressed messages file F:/quartus16.1/hld/board/test/exm_opencl_matrix_mult_x64_windows_16.01/matrix_mult/bin/matrix_mult/top.fit.smsg Error: Quartus Prime Fitter was unsuccessful. 2 errors, 261 warnings  Error: Peak virtual memory: 3462 megabytes  Error: Processing ended: Thu May 11 10:52:45 2017  Error: Elapsed time: 00:15:22  Error: Total CPU time (on all processors): 00:24:57 Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 2196 warnings Error: Flow compile (for project F:/quartus16.1/hld/board/test/exm_opencl_matrix_mult_x64_windows_16.01/matrix_mult/bin/matrix_mult/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.   Error (23031): Evaluation of Tcl script f:/quartus16.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 11 errors, 2196 warnings  Error: Peak virtual memory: 506 megabytes  Error: Processing ended: Thu May 11 10:52:46 2017  Error: Elapsed time: 00:37:33  Error: Total CPU time (on all processors): 00:00:12 --------------------------------------------------------------  I have the kernel file BLOCK_SIZE reduced to 8, the original is 64 __attribute ((reqd_work_group_size (BLOCK_SIZE, BLOCK_SIZE, 1))), I think the resources should not be out of it, why would this error? Does anyone know how to fix it? Thank you!   + ------------------------------------------------- ------------------- + ; Estimated Resource Usage Summary; + ---------------------------------------- + -------- ------------------- + ; Resource + Usage; + ---------------------------------------- + -------- ------------------- + ; Logic utilization; 55%; ; ALUTs; 33%; ; Dedicated logic registers; 25%; ; Memory blocks; 37%; ; DSP blocks; 36%; + ---------------------------------------- + -------- -------------------;

[Altera_Forum]

Check the "top.fit.summary" file, that should tell you which resource is running out. The prediction you get from the OpenCL compiler is not very accurate. You can also reduce the SIMD factor to reduce the area overhead.

[Altera_Forum]

--- Quote Start ---  Check the "top.fit.summary" file, that should tell you which resource is running out. The prediction you get from the OpenCL compiler is not very accurate. You can also reduce the SIMD factor to reduce the area overhead.  --- Quote End ---    In the file you said, I did find that the resources were out of the board. Logic utilization (in ALMs) : 20,592 / 15,880 ( 130 % ) ------------------------------------------------------  But the official example sets BLOCK_SIZE to 64. Is not my development board resources enough? If I want to increase the size of the matrix, should I modify the host or kernel file? I understand that BLOCK_SIZE should be the size of the workgroup, I found in the host file the following code: Unsigned A_height = 32 * BLOCK_SIZE; Unsigned A_width = 16 * BLOCK_SIZE; Const unsigned & B_height = A_width; Unsigned B_width = 16 * BLOCK_SIZE; Const unsigned & C_height = A_height; Const unsigned & C_width = B_width; Is it possible to understand: I set the matrix size in the host file into the kernel file, and then altera opencl sdk kernel file optimization into rtl circuit? Sorry to bother you!

[Altera_Forum]

The matrix multiplication example is designed for Stratix V FPGAs and above, your board has a much smaller Cyclone IV FPGA and hence, the default BLOCK_SIZE will not work for you. You don't need to modify the host code or the kernel code to increase the matrix size, this can be done by adding -ah=XXX -aw=XXX -bw=XXX to the command line when you want to run the host code. The example has a readme file which details how you can change BLOCK_SIZE, SIMD size and input matrix size.

[Altera_Forum]

--- Quote Start ---  The matrix multiplication example is designed for Stratix V FPGAs and above, your board has a much smaller Cyclone IV FPGA and hence, the default BLOCK_SIZE will not work for you. You don't need to modify the host code or the kernel code to increase the matrix size, this can be done by adding -ah=XXX -aw=XXX -bw=XXX to the command line when you want to run the host code. The example has a readme file which details how you can change BLOCK_SIZE, SIMD size and input matrix size.  --- Quote End ---    Thank you for your help, I have never noticed this document before. Otherwise,if I want to briefly understand how ALTERA OPENCL SDK compiles the kernel file,how do you think it should be better start?Maybe getting started by reading the matrix_mult.v?But I think it a lot complex to me .Thanks again!

[Altera_Forum]

Reading the Verilog files generated by the OpenCL compiler is a waste of time. They are machine generated and far too big and complex for the average FPGA programmer. I recommend reading the "Intel FPGA SDK for OpenCL Programming Guide" and "Intel FPGA SDK for OpenCL Best Practices Guide" and fully understanding them, and then starting to write your own kernels and applying different optimizations and checking the compilation and area report to get some idea of how the compiler works.