Dear Sir,
I am trying testbench code.But it seem above error.
I make clock scaler bench.
Would you tell me how to solve it?
Code is below:
testbench.v:
module clocktp;
reg clk;
reg res;
wire pre;
parameter STEP = 1000;
always begin
clk = 0;# (STEP/2);
clk = 1;# (STEP/2);
end
clk_scaler A1 (clk,res,pre);
initial begin
res = 1;# STEP res = 0;# STEP $stop;
end
endmodule
clock_scaler.v:
`include "defines.v"
module clk_scaler(
input clk, //clk is basic clock
input reset,
output clk_cpu
);
reg [25:0] cnt = 26'd0;
always @(posedge clk,posedge reset)
begin
if (reset)
cnt <= 26'd0;
//clk_cpu <= 0;
else if (cnt == `CPU_CLOCK) //CPU_CLOCK is 26'd49999999
cnt <= 26'd0;
else
cnt <= cnt + 26'd1;
end
assign clk_cpu = cnt < (`CPU_CLOCK / 2);
endmodule
sincerely
