Error (272006): The Logical Element multiplier implementation cannot be used together

[Altera_Forum]

I have a compiling problem when I added something in Assignment Editor. I've tried to google it but only got unrelated PDFs. 

 What I try to do is to implement the multiplier in logic elements instead of embedded multipliers, like DSP blocks.  There are two IP components in my project: LPM_MULT(named as "mult") and RAM:2-PORT(named as "ram"). My Quartus Prime Version is 16.1 and I'm using Cyclone V GX Starter Kit. The top level Verilog file is in the attachment.  The two assignments I added are as follows: https://alteraforum.com/forum/attachment.php?attachmentid=13424&stc=1   If I compile it, it will fail in "analysis and elaborate" and report the error message:"error (272006): the logical element multiplier implementation cannot be used together with synchronous clear signal for lpm_mult." I've tried to set "Implementation" to "Use Logic Elements" in "Parameter Editor" but it will cause problems with the RAM IP. How can I solve it?  Just in case the link to the verilog file breaks again, here's my code: module pipemult(  clk1,  wren,  dataa,  datab,  rdaddress,  wraddress,  q );   input clk1; input wren; input [7:0] dataa; input [7:0] datab; input [4:0] rdaddress; input [4:0] wraddress; output [15:0] q;   reg [15:0] q; wire [15:0] mult_to_ram, ram_out;     // Insert multiplier instantiation here     ram ram_inst  (.clock(clk1),  .wren(wren),  .data(mult_to_ram),  .rdaddress(rdaddress),  .wraddress(wraddress),  .q(ram_out));   mult mult_inst(  .clock(clk1),  .dataa(dataa),  .datab(datab),  .result(mult_to_ram));   always @ (posedge clk1)  q <= ram_out;   endmodule

[Altera_Forum]

The link to your code is broken, but the error is saying that you can implement the multiplier using logic instead of a DSP block, but you can't use synchronous clear for the multiplier in this implementation. Without seeing the code, it's not clear why, but this may be an architecture limitation of the Cyclone V device.

[Altera_Forum]

--- Quote Start ---  The link to your code is broken, but the error is saying that you can implement the multiplier using logic instead of a DSP block, but you can't use synchronous clear for the multiplier in this implementation. Without seeing the code, it's not clear why, but this may be an architecture limitation of the Cyclone V device.  --- Quote End ---    Just in case it breaks again, here's my code:  module pipemult(  clk1,  wren,  dataa,  datab,  rdaddress,  wraddress,  q );  input clk1; input wren; input [7:0] dataa; input [7:0] datab; input [4:0] rdaddress; input [4:0] wraddress; output [15:0] q;  reg [15:0] q; wire [15:0] mult_to_ram, ram_out;   // Insert multiplier instantiation here   ram ram_inst  (.clock(clk1),  .wren(wren),  .data(mult_to_ram),  .rdaddress(rdaddress),  .wraddress(wraddress),  .q(ram_out));   mult mult_inst(  .clock(clk1),  .dataa(dataa),  .datab(datab),  .result(mult_to_ram));  always @ (posedge clk1)  q <= ram_out;  endmodule

[Altera_Forum]

Hi, 

Which quartus version you are using currently for above issue ? There may be issue with Quartus 16.1 while you take logic elements with DSP blocks for implementing LPM_MULT from megawizard.  but it is working in 16.0.  So, it may be helpful by knowing your quartus version.