Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15465 Discussions

Error Code (121014): Net HEX2, HEX1, HEX0 cannot be assigned to more than one value. If someone can help that would be greatly appreciated.

AFera1
Beginner
348 Views

module bcd_seven_seg(SW,HEX0,HEX1,HEX2,LEDG);

input [9:0] SW;

output [6:0] HEX0, HEX1, HEX2;

output [9:0] LEDG;

wire [6:0] hex0,hex1,hex2;

assign HEX0 = ~hex0;

assign HEX1 = ~hex1;

assign HEX2 = ~hex2;

bcd_seven_seg_behavioral u0(SW[3:0],HEX0);

bcd_seven_seg_behavioral u1(SW[7:4],HEX1);

bcd_seven_seg_behavioral u2(SW[9:8],HEX2);

endmodule

module bcd_seven_seg_behavioral(bcd,hex);

input [3:0] bcd;

output reg [6:0] hex;

always @ (bcd) begin 

case(bcd)

4'b0000: hex <= 7'b0111111; 

4'b0001: hex <= 7'b0000110; 

4'b0010: hex <= 7'b1011011; 

4'b0011: hex <= 7'b1001111; 

4'b0100: hex <= 7'b1100110; 

4'b0101: hex <= 7'b1101101; 

4'b0110: hex <= 7'b1111101; 

4'b0111: hex <= 7'b0000111; 

4'b1000: hex <= 7'b1111111;

4'b1001: hex <= 7'b1100111; 

4'b1010: hex <= 7'b1110111; 

4'b1011: hex <= 7'b1111100; 

4'b1100: hex <= 7'b0111001; 

4'b1101: hex <= 7'b1011110; 

4'b1110: hex <= 7'b1111001; 

4'b1111: hex <= 7'b1110001; 

endcase 

end

endmodule 

0 Kudos
1 Reply
ak6dn
Valued Contributor III
176 Views

On these lines:

bcd_seven_seg_behavioral u0(SW[3:0],HEX0);

bcd_seven_seg_behavioral u1(SW[7:4],HEX1);

bcd_seven_seg_behavioral u2(SW[9:8],HEX2);

the second arg HEXn is an OUTPUT of this function.

And nowhere do you assign a value to 'hexN' before using it.

 

I think the above lines want to be:

bcd_seven_seg_behavioral u0(SW[3:0],hex0);

bcd_seven_seg_behavioral u1(SW[7:4],hex1);

bcd_seven_seg_behavioral u2(SW[9:8],hex2);

otherwise you are assigning a value to HEXn via the assign statements, and also the bcd_seven_seg_behavioral module output.

 

Note verilog is a case sensitive language.

 

Reply