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Error:Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints 2 pins

Shwetha_G_S
Beginner
156 Views

We use "10AS048E3F29I2SG" device, and in our hw design,FPGA uses shared I/O as following:

FPGA_RTC_FAN_SENSOR_SDA    @D20 (SHARED_Q1_5)
FPGA_RTC_FAN_SENSOR_SCL     @E20 (SHARED_Q1_6)

We are trying to map the pins to FPGA region(in pin planner),but both pins will map to that particular location then while compiling,fitter error occurs.Pin assignment is correct.

But then building project,it fails to fitter due to below error:


Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the sub messages, and then rerun the Fitter. The Altera Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.


Error (175020): The Fitter cannot place logic pin in region (78, 146) to (78, 147), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): FPGA_RTC_FAN_SENSOR_SCL
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad FPGA_RTC_FAN_SENSOR_SCL is constrained to the location PIN_E20 due to: User Location Constraints (PIN_E20)
Info (14709): The constrained I/O pad is contained within this pin
Error (175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)
Info (175029): E20


Error (175020): The Fitter cannot place logic pin in region (78, 146) to (78, 147), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): FPGA_RTC_FAN_SENSOR_SDA
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad FPGA_RTC_FAN_SENSOR_SDA is constrained to the location PIN_D20 due to: User Location Constraints (PIN_D20)
Info (14709): The constrained I/O pad is contained within this pin
Error (175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)
Info (175029): D20
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.


Error:
Error: Quartus Prime Fitter was unsuccessful. 10 errors, 167 warnings
Error: Peak virtual memory: 7796 megabytes
Error: Processing ended: Fri Jan 13 09:09:43 2023
Error: Elapsed time: 00:01:39
Error: Total CPU time (on all processors): 00:01:33

 

Please give a solution as soon as possible.

0 Kudos
5 Replies
sstrell
Honored Contributor III
139 Views

Are these pins part of some IP that is making these pin location assignments itself?  Have you tried removing the manual Pin Planner assignments you made as noted?

Shwetha_G_S
Beginner
103 Views

Hello Sir,

We have tried with removing pin planner assignments also,same error exists(fitter error).

FPGA_RTC_FAN_SENSOR_SDA and FPGA_RTC_FAN_SENSOR_SCL pins are not part of IP and it is not taking pin location itself.We are assigning pins in pin planner according to our hardware.

Please give a solution for this.

aikeu
Employee
62 Views

Hi Shwetha_G_S,


Do you still require help for the issue?


Thanks.

Regards,

Aik Eu


aikeu
Employee
51 Views

Hi Shwetha_G_S,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Thanks.

Regards,

Aik Eu


Shwetha_G_S
Beginner
37 Views

In addition to the problem mentioned earlier, one more thing is there,

In the same design, by mistake LVDS signals (these will be used for 1G Ethernet Ports) are connected on those pins where Soft-CDR support is not there. Is there any solution for the same that LVDS signals can support non soft CDR mode pins ?

 

Kindly give a solution for this.

Reply