Error: The Fitter cannot add location assignment PIN T28 to node

[Altera_Forum]

Hi, 

 I am synthesizing a submodule with all pins set to VIRTUAL_PIN in the .qsf. I have logiclocked the partition (the whole design) to the top ~50% of a Stratix III. I am getting the below error.  Does anyone have any ideas what is causing this?  (Are pins from outside of the logiclocked region I specified not allowed?)  Linc-   Error: The Fitter cannot add location assignment PIN T28 to node ~ALTERA_DATA0~ with existing location assignment <nothing> Error: Can't fit design in device Error: Quartus II 64-Bit Fitter was unsuccessful. 2 errors, 55 warnings  Error: Processing ended: Mon Aug 4 20:48:17 2008  Error: Elapsed time: 00:05:13  Error: Total CPU time (on all processors): 00:03:08 Error: Quartus II Full Compilation was unsuccessful. 3 errors, 2200 warning

[Altera_Forum]

Did you add pins to the LLR, or just the top-hierarchy? To my understanding, pins are not part of an LLR unless explicitly added. That ~ALTERA_DATA0~ is a configuration pin, I believe. Actually, do you have it assigned to be Virtual? If so, then maybe it is making it an internal(virtual) pin, when in reality it has dedicated I/O functionality. If so, please remove that assignment.

[Altera_Forum]

Virtual pins were only assigned to the toplevel-module, which is also the LLR. 

~ALTERA_DATA0~ seems to be an Altera/Quartus generated pin. I have no knowledge or reference to it anywhere in the design.

[Altera_Forum]

First determine if the problem is from the LLR or the virtual pins assignment. My guess is it's the latter. If so, go to the Assignment Editor, find all the pins with the Node Finder, and make virtual pin assignments here. This is what I've always done and had success with. (Usually you don't want a bulk virtual pin assignment, i.e. clocks are real, perhaps a global reset, etc. That's not to say your case may not have those conditions, just why I've done the more manual way in the past). If that works(or whatever works), please file an SR, as what you're doing should work too.

[Altera_Forum]

--- Quote Start ---  Usually you don't want a bulk virtual pin assignment, i.e. clocks are real, perhaps a global reset, etc.  --- Quote End ---    Even if the clock input to this part of the design is not a real device pin (for example, it's driven by a PLL in the top level of the design), don't use a virtual-pin assignment for it. The Quartus handbook says not to use virtual pins for clocks. There are a few more cases too that don't support virtual pins.  From Volume 2, Section III, Chapter 10:    --- Quote Start ---  Bidirectional, registered I/O pins, and I/O pins with output enable signals cannot be virtual pins.  ...  Use the following guidelines for creating virtual pins in the Quartus II software: 

• Do not declare clock pins 
• Nodes or signals that drive physical device pins in the top-level design should not be declared as virtual pins 

  --- Quote End ---  

[Altera_Forum]

I think, ~ALTERA_DATA0~ appears only as an assigned pin, when an ASMI is included in the design, e. g. referenced from SFL or a NIOS II programming function. Using this function in a logic locked region may cause the problem.

[Altera_Forum]

Thanks. 

Brad: A virtual pin was not used for clk. Rysc: What is SR? Service request?  FvM: I am not aware of using an ASMI. Here are my results. I don't have a clear solution. In the assignment editor, I deleted the ~ALTERA_DATA0~ assignment. This seemed to be the solution, but it could have been something else I inadvertantly did.

[Altera_Forum]

Yep, service request. I didn't realize you had a specific assignment to that pin. If so, I don't think an SR is necessary, as it sounds like the error message was pretty accurate. (I'm not following everything, so may be off...)