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Error: Third-party timing and resource estimation model project creation failed (Quartus 20.1)

Error: Third-party timing and resource estimation model project creation failed (Quartus 20.1)

This happens on ROM for ARRIA 10 FPGA.

Model Creation is fine for RAM.

Attaching the ROM ip that makes it fail.

 

log during creation:

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/root_components.ipx

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/root_components.ipx: Loading now from components.ipx

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/ip_component_categories.ipx

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/ip_component_categories.ipx described 0 plugins, 0 paths, in 0.01 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/ip_component_categories.ipx matched 1 files in 0.01 seconds

Info: /data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/synplify_synth_quartus_fit/ip/**/* matched 0 files in 0.00 seconds

Info: /data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/synplify_synth_quartus_fit/* matched 164 files in 0.57 seconds

Info: /data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/synplify_synth_quartus_fit/*/* matched 1074 files in 0.80 seconds

Info: /data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/quartus_synth_and_fit/* matched 9 files in 0.02 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/$$QUARTUS_IP_USERDIR/* matched 0 files in 0.00 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/$$QUARTUS_IP_GLOBALDIR/* matched 0 files in 0.00 seconds

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/altera_components.ipx

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/hw_altera_components.iipx

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/hw_altera_components.iipx described 2788 plugins, 0 paths, in 0.26 seconds

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/sw_altera_components.iipx

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/sw_altera_components.iipx described 71 plugins, 0 paths, in 0.05 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/altera_components.ipx described 0 plugins, 2 paths, in 0.31 seconds

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/toolkits.ipx

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/altera/toolkits.ipx described 18 plugins, 0 paths, in 0.02 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/ip/**/* matched 120 files in 0.35 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/ip/**/* matched 0 files in 0.00 seconds

Info: Reading index /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/builtin.ipx

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/builtin.ipx described 95 plugins, 0 paths, in 0.01 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/builtin.ipx matched 1 files in 0.01 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/quartus/common/librarian/factories/**/* matched 0 files in 0.00 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/$IP_IPX_PATH matched 1 files in 0.00 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/root_components.ipx described 0 plugins, 12 paths, in 1.75 seconds

Info: /sysmnt/cadappl_sde/ictools/quartus/20.1/qsys/lib/root_components.ipx matched 1 files in 1.75 seconds

Info: Saving generation log to /data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/synplify_synth_quartus_fit/cortex_rom1/cortex_rom1_generation.rpt

Info: Generated by version: 20.1 build 177

Info: Starting: Create HDL design files for synthesis

Info: qsys-generate /data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/synplify_synth_quartus_fit/cortex_rom1.ip --synthesis=VHDL --greybox --output-directory=/data/rfd_lib/rfd_fpga/gbb5_fpga_a_arria10_trial/synplify_synth_quartus_fit/cortex_rom1 --family="Arria 10" --part=10AS066H2F34I1SG

: cortex_rom1.rom_1port_0: Targeting device family: Arria 10.

: cortex_rom1.rom_1port_0: In 'Mem Init' tab, the initial content of the memory must be specified for a ROM.

: cortex_rom1.rom_1port_0: In 'Performance Optimization' tab, Arria 10 does not support 'Timing/Power Optimization' feature.

Info: cortex_rom1: "Transforming system: cortex_rom1"

Info: cortex_rom1: "Naming system components in system: cortex_rom1"

Info: cortex_rom1: "Processing generation queue"

Info: cortex_rom1: "Generating: cortex_rom1"

Info: cortex_rom1: "Generating: cortex_rom1_rom_1port_2010_4tireei"

Info: cortex_rom1: Done "cortex_rom1" with 2 modules, 2 files

Info: Generating third-party timing and resource estimation model ...

Error: Third-party timing and resource estimation model project creation failed: /sysmnt/cadappl_sde/ictools/quartus/20.1/quartus/linux64/quartus_sh -t quartus_greybox.tcl

Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings

Info: Finished: Create HDL design files for synthesis

 

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13 Replies
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Hi,

 

I tried to generate the HDL using the .ip file provided, the HDL is successfuly generated. I cannot replicate the same error as yours. Could you provide the full design.QAR for investigation?

 

Capture.PNG

 

Thanks.

Best regards,

KhaiY

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Novice
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No, I cannot share my project.

But could you generate all .v greybox views for synplify and attach them in this ticket?

I'm attaching my other ROMs.

 

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Novice
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No, I cannot share my project.

But could you generate all .v greybox views for synplify and attach them in this ticket?

I'm attaching my other ROMs.

 

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Novice
105 Views

posted a file.
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Hi,

 

I cannot replicate the error. Can you share the steps to reproduce the error?

 

Thanks.

Best regards,

KhaiY

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Novice
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Here is a video showing the steps:

 Removed

 

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Hi,

 

Thanks for the video. I can duplicate the error now. I will file a case to the engineering team. Thanks for reporting this error to us.

 

Thanks.

Best regards,

KhaiY

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Novice
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Great.

Can I remove the video now?

BTW, As you were able to create the ROM greybox, how did you manage to do it?

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Hi,

 

Yes. You may remove the video.

Initially, I thought the error that you had reported is on the Third Party simulation model.

 Capture.PNG

After watching the video, I tick the first check box and the error occured. I will update once I received the feedback from the team Thanks for showing the steps to reproduce the error.

 

Thanks.

Best regards,

KhaiY

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Novice
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ok!

 

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Hi,

 

The team is working on this error. Kindly untick the Clear output directories for selected generation targets to generate the HDL as a temporarty workaround.

 

Thanks.

Best regards,

KhaiY

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Novice
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Thanks for the workaround KhaiY, I will use it.

 

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Hi,

No problem. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY

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