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Hello, I am writing a verilog code from my DE10-Lite Board to scroll the a word or number but keep having errors. Would you be able to help?

module DE10_LITE_Default(

 input clock, reset,

 input HEX0, HEX1, HEX2, HEX3, //the 4 inputs for each display

 output a, b, c, d, e, f, g, dp, //the individual LED output for the seven segment along with the digital point

 output [3:0] an  // the 4 bit enable signal

 );

 

localparam N = 18;

 

reg [N-1:0]count; //the 18 bit counter which allows us to multiplex at 1000Hz

 

always @ (posedge clock or posedge reset)

 begin

 if (reset)

  count <= 0;

 else

  count <= count + 1;

 end

 

reg [6:0]sseg_temp; //the 7 bit register to hold the data to output ==== Changed from 'reg' ====

reg [3:0]an_temp; //register for the 4 bit enable

 

always @ (*)

 begin

 case(count[N-1:N-2]) //using only the 2 MSB's of the counter 

  

  2'b00 : //When the 2 MSB's are 00 enable the fourth display

  begin

   sseg = HEX0;

   an_temp = 4'b1110;

  end

  

  2'b01: //When the 2 MSB's are 01 enable the third display

  begin

   sseg = HEX1;

   an_temp = 4'b1101;

  end

  

  2'b10: //When the 2 MSB's are 10 enable the second display

  begin

   sseg = HEX2;

   an_temp = 4'b1011;

  end

   

  2'b11: //When the 2 MSB's are 11 enable the first display

  begin

   sseg = HEX3;

   an_temp = 4'b0111;

  end

 endcase

 end

assign an = an_temp;

 

 

reg [6:0] HEX_Display; // 7 bit register to hold the binary value of each input given

 

always @ (*)

 begin

 case(sseg)

  4'd0 : HEX_Display = 7'b0111111; //to display dash

  4'd1 : HEX_Display = 7'b0000001; //to display 0

  4'd2 : HEX_Display = 7'b1001111; //to display 1

  4'd3 : HEX_Display = 7'b0110000; //to display E

  4'd4 : HEX_Display = 7'b1000010; //to display d

  4'd5 : HEX_Display = 7'b0111111; //to display dash

  //4'd6 : sseg_temp = 7'b0000010; //to display 6

 // 4'd7 : sseg_temp = 7'b1111000; //to display 7

 // 4'd8 : sseg_temp = 7'b0000000; //to display 8

  //4'd9 : sseg_temp = 7'b0010000; //to display 9

  //default : sseg_temp = 7'b0111111; //dash

 endcase

 end

assign HEX_Display = {g, f, e, d, c, b, a} ; //concatenate the outputs to the register, this is just a more neat way of doing this.

// I could have done in the case statement: 4'd0 : {g, f, e, d, c, b, a} = 7'b1000000; 

// its the same thing.. write however you like it

 

assign dp = 1'b1; //since the decimal point is not needed, all 4 of them are turned off

 

 

endmodule

 

 

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Highlighted
Beginner
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Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(21) near text: "wire"; expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(74) near text: "assign"; expecting "endcase". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(74) near text: '. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(148) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(162) near text: "}"; expecting ":", or ",". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(162) near text: "{"; expecting "}". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(181) near text: "assign"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(185) near text: "endmodule"; expecting "endcase". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Info (12021): Found 0 design units, including 0 entities, in source file shift code, modified but not working yet.v

Info (144001): Generated suppressed messages file C:/Users/ceedwards/Downloads/Quartus files downloaded/DE10_LITE_Default ADD CODE to CODE STRUCTURE_project/PROJECT C HEX Modified_restored/top.map.smsg

 

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Highlighted
Moderator
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I get different errors than you did when elaborating this code. However, you have "sseg" but never define it. It should be type reg. You also make assignments to HEX_Display in two separate processes. I think you mean for HEX_Display to be on the right side of the final assign statement:

 

assign {g,f,e,d,c,b,a} = HEX_Display;

 

And since HEX0-HEX3 are single bit inputs, making sseg a single bit value, only the 0 and 1 checks in the final case statement can match to set the value of HEX_Display. This only displays warnings, not errors, when compiled but it should be fixed.

 

#iwork4intel

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Beginner
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Thank you sstrell for check my code. Can I confirm this code?

 

//////////////////// SCROLLING DE10 ////////////////////////////////

 

module DE10_LITE_Default(

 input clock, reset,

 input HEX0, HEX1, HEX2, HEX3, //the 4 inputs for each display

 output a, b, c, d, e, f, g, dp, //the individual LED output for the seven segment along with the digital point

 output [3:0] an  // the 4 bit enable signal

 );

 

localparam N = 18;

 

reg [N-1:0]count; //the 18 bit counter which allows us to multiplex at 1000Hz

 

reg [6:0]sseg; // NEW CODE

 

always @ (posedge clock or posedge reset)

 begin

 if (reset)

  count <= 0;

 else

  count <= count + 1;

 end

 

reg [6:0]sseg_temp; //the 7 bit register to hold the data to output ==== Changed from 'reg' ====

reg [3:0]an_temp; //register for the 4 bit enable

 

always @ (*)

 begin

 case(count[N-1:N-2]) //using only the 2 MSB's of the counter 

  

  2'b00 : //When the 2 MSB's are 00 enable the fourth display

  begin

   sseg = HEX0;

   an_temp = 4'b1110;

  end

  

  2'b01: //When the 2 MSB's are 01 enable the third display

  begin

   sseg = HEX1;

   an_temp = 4'b1101;

  end

  

  2'b10: //When the 2 MSB's are 10 enable the second display

  begin

   sseg = HEX2;

   an_temp = 4'b1011;

  end

   

  2'b11: //When the 2 MSB's are 11 enable the first display

  begin

   sseg = HEX3;

   an_temp = 4'b0111;

  end

 endcase

 end

assign an = an_temp;

 

 

reg [6:0] HEX_Display; // 7 bit register to hold the binary value of each input given

 

always @ (*)

 begin

 case(sseg)

  4'd0 : HEX_Display = 7'b0111111; //to display dash

  4'd1 : HEX_Display = 7'b0000001; //to display 0

  4'd2 : HEX_Display = 7'b1001111; //to display 1

  4'd3 : HEX_Display = 7'b0110000; //to display E

  4'd4 : HEX_Display = 7'b1000010; //to display d

  4'd5 : HEX_Display = 7'b0111111; //to display dash

  //4'd6 : sseg_temp = 7'b0000010; //to display 6

 // 4'd7 : sseg_temp = 7'b1111000; //to display 7

 // 4'd8 : sseg_temp = 7'b0000000; //to display 8

  //4'd9 : sseg_temp = 7'b0010000; //to display 9

  //default : sseg_temp = 7'b0111111; //dash

 endcase

 end

 

 assign {g,f,e,d,c,b,a} = HEX_Display; // CHANGED FROM THIS assign HEX_Display = {g, f, e, d, c, b, a} ;

 //concatenate the outputs to the register, this is just a more neat way of doing this.

// I could have done in the case statement: 4'd0 : {g, f, e, d, c, b, a} = 7'b1000000; 

// its the same thing.. write however you like it

 

assign dp = 1'b1; //since the decimal point is not needed, all 4 of them are turned off

 

assign {g,f,e,d,c,b,a} = HEX_Display; // CHANGED FROM THIS assign HEX_Display = {g, f, e, d, c, b, a} ;

 //concatenate the outputs to the register, this is just a more neat way of doing this.

// I could have done in the case statement: 4'd0 : {g, f, e, d, c, b, a} = 7'b1000000; 

// its the same thing.. write however you like it

 

endmodule

 

 

COMPILING RESULTS;

 

Info (12021): Found 3 design units, including 3 entities, in source file project c hex display.v

Info (12023): Found entity 1: part1

Info (12023): Found entity 2: mux_3bit_5to1

Info (12023): Found entity 3: char_7seg

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(21) near text: "wire"; expecting a direction.

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(74) near text: "assign"; expecting "endcase".

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(74) near text: '.

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(148) near text: ")"; mismatched closing parenthesis .

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(162) near text: "}"; expecting ":", or ",".

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(162) near text: "{"; expecting "}".

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(181) near text: "assign"; expecting an operand.

 

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(185) near text: "endmodule"; expecting "endcase".

 

Info (12021): Found 0 design units, including 0 entities, in source file shift code, modified but not working yet.v

Info (144001): Generated suppressed messages file C:/Users/ceedwards/Downloads/Quartus files downloaded/DE10_LITE_Default ADD CODE to CODE STRUCTURE_project/PROJECT C HEX Modified_restored/top.map.smsg

 

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Highlighted
Moderator
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You're now assigning single bit values (HEX0-HEX3) to a 7-bit signal (sseg), so again, your final case statement is only going to work for sseg equal to 0 or 1. Is your case statement supposed to be checking an_temp instead of sseg? That would make more sense. If so sseg is not even needed. Or are you saying that HEX0-HEX3 are supposed to be 4 bit inputs each, like HEX0[3:0] for the first one? It's really not clear what you're trying to do here.

 

And the errors you've posted don't look like they correspond to this file. They reference some other file named "yet.v" that you haven't posted. The giveaway: "wire" in the first error which isn't even in the code you've posted. Double-click errors to open the correct file and the text editor will highlight where the error is.

 

#iwork4intel

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Highlighted
Employee
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Hello Krose13,


Did the solutions that Sstrell works for you?

Still having issues with your code?


Best regards.


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