Error building SOPC RTL simulation model

[Altera_Forum]

Hi, 

 I have been running through the "Designing with the Nios II Processor and SOPC Builder" tutorial and the accompanying Lab exercises. Things has been going well, both the hardware has been built and the software example, with simple.c, has been running on the FPGA. (Lab 1 and 2).  But in Lab 3, concerning RTL simulation, I have run into a problem. Whenever I run the SOPC Builder Generate command with VHDL simulation model enabled, I get the following error:  Error: Family name "stratix" is illegal  I have the Nios II Embedded Evaluation Kit with the Cyclone III EP3C25 FPGA. The Quartus project is set up as a Cyclone III family, and in the SOPC Builder the Target is set up as Device Family: Cyclone III. I have run the setup tcl script: Setup_Cyclone_3C25.tcl and the family setup in my default assignment file (niosII_lab_assignment_defaults.qdf) is:  set_global_assignment -name FAMILY "Cyclone III"  However when I press the "Generate" button in SOPC Builder, it generates a temporary directory: simgen_tmp_0 and in this directory I can see among other things, the file: cpu.qsf and one of the first lines in this file is:  set_global_assignment -name family stratix  I can not see where this change of the FAMILY variable is coming from, or indeed if this is the cause of the problem.  Has anyone else seen this problem? Or have an idea about how I proceed from here?  Best regards  Jens Seiersen  Computer Setup: Window 7 Professional 64-bit Quartus II Version 10.0 Build 262, Service Pack 1 ModelSim Altera Start Edition 6.5e

[Altera_Forum]

there were some problems with 10.0 where Quartus II had dependencies on the Stratix or Stratix II libraries, so if you chose not to install the Stratix families you may run into problems like this. i think things are better in 10.1 

 which families did you install? can you upgrade to 10.1? ModelSim-A(S)E doesn't support Windows 7 until this release, so its another good reason to upgrade

[Altera_Forum]

Hi, again 

 Thank you for the pointer. It helped, updating my tool suite to 10.1. Now I can run RTL simulations of my FPGA/NIOS designs.  Now if only the tutorial material could be updated to version 10.1 it would be a bit easier reading the lab-screenshots.  Thank you for your help.  - Jens