Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Error:illegal defpram

Altera_Forum
Honored Contributor II
1,132 Views

Hi, 

 

I am using Synplify pro as synthesis tool inside the quartus(Altera tool). I am a new user for Synplify pro. while syntheising I am getting following errors for Altera transreceivers cores. 

 

Illegal defparam. parameter fast_lock_control can not be found in module stratixiv_hssi_pll.  

 

I checked that this parameter is not in the library file stratixiv.v of synplify pro tool.  

 

 

Can anyone please tell me how to fix it?
0 Kudos
0 Replies
Reply