Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Error in compling

FTecc
Beginner
1,045 Views

problem.jpg

 

When I compile this program I get the errors in the photo. Can someone help me?

The program is a demo file and I didn't make any changes. The manufacturer has assured me that it is fully functional.

Use of first quartus 18.0.

I tried also with quartus II and I have the same problem

😭

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RRomano001
New Contributor I
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Please provide more detail, which board which demo design which vendor?

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FTecc
Beginner
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yes, the board is Altera De4 board equipped with Fpga Stratix IV EP4SGX230KF40C2.

The external card is terasic SDI- HSMC p0039.

I download the demo project by official site.

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RRomano001
New Contributor I
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from main board and add on I suppose demo is

PCIe Image Process Application.

I am no more using stratix, require subscription, mine expired more than 10yr ago, hope someone else can help you.

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sstrell
Honored Contributor III
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The design was probably created in an older version of Quartus that used those settings for Signal Tap. The easiest thing to try would be to open the project, open the .stp file, and save it as a new .stp file. Then in Quartus, go to Assignments-> Settings-> Signal Tap and point to the new file. That should fix things. Then try to recompile.

 

#iwork4intel

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