Error << TOP-LEVEL>>

[Altera_Forum]

Hi, 

I'm a new user to Quartus ii and i have a trouble when i m tring to do a syntesis and analysis for my circuit ;   I have a message like error: Top-Level design entity "name of project" is undifined.   Thank you for helping me to solve this probelme     thanks

[Altera_Forum]

Do you have a verilog module or a VHDL entity named "name of project" ? 

Is that file included in the project ?

[Altera_Forum]

Thanks for helping me. it is a VHDL entity. I have the entity name same to the TOP_LEVEL. (on time was worked and now i have the same Error :eek:) 

 What do you think  Thanks

[Altera_Forum]

So the file that has the "TOP_LEVEL" entity is included in your project ? 

And the "TOP_LEVEL" entity is selected as top-level in Quartus ?