Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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16025 Discussions

Error: one_0.cpu_one: Multiplier selected is not compatible with selected device and design type


Hi everyone!


I'm trying to implement multiprocessor system design explained in Multiprocessor Nios II System Tutorial( When I try to add philosopher subsystems into my main system it says that multiplier selected is not compatible with selected device. I have no idea what that means and how to solve this problem. The device that I'm using is MAX10 NEEK 10m50daf484c6ges and Multiprocessor Tutorial version v1 readme.txt says that this design also requires  Altera Cyclone III 3C120 Development Board, which isn't the same development board that I have.

I would be very grateful if someone could help me solve this problem.




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3 Replies
Valued Contributor II

Are you using the Qsys / Platform designer files provided in the example or building your own from scratch? I suggest you select the NIOS CPU in the system and check the frequency settings, Make sure the frequency is within operating range of the MAx10 FPGA your're using. Did you also change the Device setup in the main project settings?


Hello Abe!


Thanks for your replying!


I'm using Qsys / Platform designer files provided in the example. When I was starting to add soft CPUs to the main system Qsys started complaining about incompatible multipliers. I checked NIOS 2 CPU and the frequency is 50MHz as it was recommended by the tutorial. By the way, the compilation of the file worked nice but adding soft CPUs to the system caused incompatibility errors. Yes, the device setup is also changed so everything is fine in the setup.



Valued Contributor II

This error happens coz the IP's referenced in the design are outdated v10/11 and needs to be updated. To get around this you will have to manually upgrade and regenerate all of the philosopher systems.


  1. Load the entire design (top-level Qsys file and other Qsys subsystem files) along with the rest of the HDL modules into Quartus.
  2. In the Project Navigator Pane, select Files or IP Units . This will now show the 4 Philosopher subsystems along with the main system.
  3. Double-click a single subsystem to open it. This will force Qsys to regenerate the IPs in the design and upgrade them.
  4. When the design is open, select the CPU in each subsystem and open its Properties in the right pane.
  5. Here select the NIOS-2/e CPU instead of NIOS-2/f.
  6. Click Finish button, and then Save the subsystem.
  7. Generate the subsystem and close it.
  8. Perform the same for the rest of the subsystems as well as for the main CPU.
  9. Change the CPU to NIOS-2/e and regenerate.
  10. You will also have to comment out the fsa and fsd ports in the top-level.v HDL file.
  11. You will also have to re-assign the pins to the correct values on the MAX10 FPGA board. You can remove all other Pin assignments and keep only the ones used in the top-level file.
  12. Save the file and then Compile the whole design.


This should get it working.