I changed an existing schematic. I renamed few ports and reassigned to some FPGA pins and deleted many other ports. Some ports in schematic are showing the pin number that I assigned to them in pin planner, but others are not. Can any body please inform what to change in order to display all the pin assignments in schematic.
After making any logic changes, you have to run the Analysis & Synthesis flow for the updated ports to show up in pin planner. Run the flow, then come back to the pin planner and check / assign the pins again.
Actually in pin planner, every pin is visible. But in Schematic(bdf), some pin assignments are visible while others are not. Why some are visible and others are not. I have run the analysis process. Cleaned the QSF file. But still cant see the pin tags in Schematics for few ports. See the file in the attachment please.
"Actually in pin planner, every pin is visible. But in Schematic(bdf), some pin assignments are visible while others are not."
Can you please provide following information?
- what does this mean pins visible in schematic?
- provide screenshots of original & modified schematic (where some pins are not visible) window.
(This message was posted on behalf of Intel Corporation)
1) The pin tags, which means for example this net is connected to that pin number on FPGA. The tags, that are visible on schematic after we assign a particular net to a pin in pin planner.
2) Please see the screen shots provided on this thread in earlier posts. All the nets are connected in pin planner, but only few are visible in Schematic i.e PIN_23 and PIN_105.