Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

FPGA Reset

SKhan10
Novice
1,202 Views

Hallo

For our project, we are using a combination Simulink HDL coder and Quartas to generate vhdl files and program the FPGA. We create our design in Simulink and using the Simulink HDL coder we generate the VHDL files. Then we use this vhdl files to create a project in Quartus and then download it in the FPGA.

We are using an Asynchronous reset. But from Quartus we get the following message

 

Rule R102: External reset signals should be synchronized using two cascaded registers

 

I have looked through the forum and understood that we need to create 2 D-flip flops to solve this problem. But Simulink HDL coder does not allow to use a D flip flop on the design. Any idea how this problem can be solved?

 

 

0 Kudos
2 Replies
Tricky
New Contributor II
195 Views

D Flip flops are just Z-1 transforms in simulink.

But you might be better treating the simulink design as a block you instatiate manually in some hand coded VHDL to handle all the IO.

GuaBin_N_Intel
Employee
195 Views

After converting into VHDL file, you can simply add sync register chain as following ​https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/quartus2/qts_qii51006.pdf... 9-14.

Reply