I have a simple 32-bit counter. The design works fine at the RTL level. I have generated the gate level of this counter .vo file.
I have changed the Makefile to accomadate the gate level simulation.
I am using a Makefile for the process of compilation and simulation.
I have used vlib and vmap to define and remap the libraries used in the design.
I have used the vlog and vopt to compile and optimize the design. It all went through ok.
I have used vsim to simulate, unfortunatelly, I have got the following error(s) in vsim,
Here is the run for the vopt and vsim,
vopt -sv -timescale 1ns/1ps -L work -L rtl_sv_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -modelsimini ./modelsim.ini -o cntr_32_async_opt top
Top level modules:
-- Loading module top
-- Loading module cntr_32_async
-- Loading module cyclonev_ver.cyclone10gx_lcell_comb
Optimizing 6 design-units (inlining 1/2 module instances, 65/65 cell instances):
-- Inlining module cyclonev_ver.cyclone10gx_lcell_comb(fast)
-- Inlining module cyclonev_ver.cyclone10gx_lcell_comb(fast__1)
-- Inlining module cyclonev_ver.cyclone10gx_lcell_comb(fast__2)
-- Inlining module cyclonev_ver.cyclone10gx_lcell_comb(fast__3)
-- Inlining module cntr_32_async(fast)
-- Optimizing module top(fast)
Optimized design name is cntr_32_async_opt
End time: 20:34:37 on Sep 23,2022, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
vsim -c -modelsimini ./modelsim.ini -L work_lib -L work -L rtl_sv_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -permit_unmatched_virtual_intf -displaymsgmode both -sv_seed 0 -do "view structure; view signals;" cntr_32_async_opt rtl_sv_lib.top
# vsim -c -modelsimini ./modelsim.ini -L work_lib -L work -L rtl_sv_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -permit_unmatched_virtual_intf -displaymsgmode both -sv_seed 0 -do "view structure; view signals;" cntr_32_async_opt rtl_sv_lib.top
# Start time: 20:35:55 on Sep 23,2022
# ** Warning: (vsim-3824) Optimized (cntr_32_async_opt) and unoptimized (top) top-level design units are
# simulated together. Unoptimized design units will not be optimized.
# ** Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
# Error loading design
Error loading design
# End time: 20:35:55 on Sep 23,2022, Elapsed time: 0:00:00
# Errors: 1, Warnings: 1
make: *** [Makefile:61: run] Error 12
Any idea to the cause of this error.
Thank you in advance,
questa_fe is used for vlib,vmap,vlog,vopt, & vsim
Here is the system variable setting,
QUARTUS_INSTALL_DIR := "......./intelFPGA_pro/22.1/quartus"
QSYS_SIMDIR := ........./Test/cntr_32_async
TOP_LEVEL_NAME := "top"
Here is the format of vlog used as an example,
vlog -work altera_ver -sv /home/aballou/intelFPGA_pro/22.1/quartus/eda/sim_lib/altera_primitives.v
In questa the -novopt will no longer supported in Questa, You can delete it and rerun the simulation. In the Simulation Waveform Editor, choose Simulation Settings|Simulation Options and delete -novopt following vsim in the Model Script (and save the changes).
Thanks SyafieqS for your input.
I have looked for your suggestion -novopt in vsim waveform and it is not there.
I have attached the version of vsim that I have and running. Also, I have attached the options available in the wave editor.
As you see from both screen shots, I have gone through simulate options and compile options and both have nothing about -novopt.
Compile option has vopt flow option which is selected.
I have spend a lot of time to resolve this issue and I have tried different things and always get this error of vsim-12110.
I appreciate your help. Please advice how to move forward with this issue. As stated in this thread, vsim works ok with rtl simulation. The issue is showing with gate level simulation and inluding gates from Altera library. Please let me know if a Zoom meeting is possible.
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