FIFO Outputs all HiZ in RTL Simulation

Altera_Forum · ‎02-16-2016

Hi All,

I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct.

However, when I try to simulate an Altera Megafunction (DCFIFO in this case) all of the outputs are always HiZ no matter what inputs I give. I have done a lot of searching but I haven't come across anything which solved my problem. All of the other threads I found usually conclude with "Add the libraries", but I have done that. The code compiles fine. I'm running the simulation with "vsim work.sync_fifo -L altera_mf"

Output screenshot is attached.

After looking into the generated code it seems like the Megawizard just generates wrappers. How do I get the actual internals to simulate?

I also understand the during synthesis a lot of optimization happens. Outputs which are not depended on by the rest of the design get removed. But if I am simulating the module directly, this should not happen, correct?

Thanks

Altera_Forum · ‎02-16-2016

From the attached waveform, it seems you have tied the FIFO reset signal to one. I think its reset signal is active-high; If so, drive it with '1', and after a few clock cycles drive it with '0'.

More over, issue some write request signals, so that something would be written into it.

Altera_Forum · ‎02-16-2016

What did you put in the testbench? It looks like there is nothing more than a clock and a reset stuck at 1

Altera_Forum · ‎02-16-2016

Right now the test bench IS just a clock signal. I added in a reset to 1 in that screenshot just to try it out. Whether it is 1 or 0, the outputs are still HiZ. I also tried what msj suggested, which was drive reset to 1 for a few clocks, then drive to 0. Still no change.

I have also tried some write signals previously. Here's another screenshot. I think this should write 5 bytes of 8'b10101010 to the FIFO. Is this wrong?

Altera_Forum · ‎02-16-2016

have you actually connected the clock to the FIFO? how about the other signals?

Post the testbench code?

Altera_Forum · ‎02-16-2016

what is clock frequency? Are you simulating a post-place & route design or a pre-synthesis one?

you'd better post your code.

Altera_Forum · ‎02-16-2016

I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output.

`timescale 1ns / 100ps
module sync_fifo_tb ();
  
  //
  // Inputs to module
  reg clk;
  reg wrreq;
  reg rdreq;
  reg data;
  reg sclr;
  
  //
  // Outputs from module
  wire q;
  wire usedw;
  wire full;
  wire empty;
  
  //
  // Instantiate device
  sync_fifo U1(
        .clock(clk),
        .data(data),
        .rdreq(rdreq),
        .sclr(sclr),
        .wrreq(wrreq),
        .empty(empty),
        .full(full),
        .q(q),
        .usedw(usedw)
        );
        
  //
  // Clock setup
  always
   # 5 clk = ~clk;
  
  //
  // Initial setup
  initial
  begin
    clk = 0;
    sclr = 1;
    wrreq = 0;
    rdreq = 0;
    data = 8'b10101010;
    
   # 50 sclr = 0;
    
   # 20 wrreq = 1;
    @(posedge clk); // Wait 5 clocks
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
   # 5 wrreq = 0;
  end
  
endmodule

Altera_Forum · ‎02-16-2016

I posted a test bench file, but that is awaiting moderation for some reason. In the meantime, I'm not entirely sure how to answer that question msj.

I am opening the Verilog files in a ModelSim project and compiling them there. I am then running the vsim command on the module itself. The module was generated using the Quartus II Megawizard. There is no code of my own, except for the test bench.

I don't think this is a problem with code though. This problem is occurring for any of the generated megafunctions. Even when I try to simulate a PLL megafunction, which takes no inputs but a 50MHz clock, has HiZ outputs. I must be doing something else wrong, but I have no idea what it might be.

Altera_Forum · ‎02-16-2016

meanwhile, run simulator without optimization:

vsim -novopt work.sync_...

Altera_Forum · ‎02-16-2016

"vsim -novopt work.sync_fifo_tb -L altera_mf" produces no change. I even recompiled with -O0 first.

Altera_Forum · ‎02-16-2016

--- Quote Start ---

I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output.

--- Quote End ---

Ive unblocked all your posts - posting code with low post numbers requires moderation.

No, that is a perfectly normal thing to do (and much better than running it from quartus).

Have you compiled the sync_fifo block? where is the code for that?

Altera_Forum · ‎02-16-2016

I have added both the sync_fifo.v and sync_fifo_bb.v files, generated from the wizard, into my ModelSim project. They both compile fine, along with my test bench.

Here is the code for sync_fifo.v:

// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo 
// ============================================================
// File Name: sync_fifo.v
// Megafunction Name(s):
// 			scfifo
//
// Simulation Library Files(s):
// 			
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sync_fifo (
	clock,
	data,
	rdreq,
	sclr,
	wrreq,
	empty,
	full,
	q,
	usedw);
	input	  clock;
	input	  data;
	input	  rdreq;
	input	  sclr;
	input	  wrreq;
	output	  empty;
	output	  full;
	output	  q;
	output	  usedw;
	wire  sub_wire0;
	wire  sub_wire1;
	wire  sub_wire2;
	wire  sub_wire3;
	wire  usedw = sub_wire0;
	wire  empty = sub_wire1;
	wire  full = sub_wire2;
	wire  q = sub_wire3;
	scfifo	scfifo_component (
				.clock (clock),
				.sclr (sclr),
				.wrreq (wrreq),
				.data (data),
				.rdreq (rdreq),
				.usedw (sub_wire0),
				.empty (sub_wire1),
				.full (sub_wire2),
				.q (sub_wire3),
				.aclr (),
				.almost_empty (),
				.almost_full ());
	defparam
		scfifo_component.add_ram_output_register = "OFF",
		scfifo_component.intended_device_family = "Cyclone II",
		scfifo_component.lpm_numwords = 2048,
		scfifo_component.lpm_showahead = "OFF",
		scfifo_component.lpm_type = "scfifo",
		scfifo_component.lpm_width = 8,
		scfifo_component.lpm_widthu = 11,
		scfifo_component.overflow_checking = "ON",
		scfifo_component.underflow_checking = "ON",
		scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL "usedw"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_fifo_bb.v TRUE

Altera_Forum · ‎02-17-2016

Generated wrapper and blackbox files are attached. After looking at these, it really looks like there's nothing actually "executable" in here. How does ModelSim know where to go to find the actual circuit?

Altera_Forum · ‎02-17-2016

The black box is no use to you - it is just there as a top level file for the interfaces - it has no functionality (hence black box). Are you simulating this file?

Altera_Forum · ‎02-17-2016

No, I am simulating the sync_fifo.v file.

It appears that all this file does is instantiate and wire up an scfifo. Could it be that this file is missing from my project? I have no idea where to find it so I can add it and compile. But if that were the case, how would sync_fifo.v compile at all?

e: Interestingly, if I remove the sync_fifo_bb.v file, I cannot start a simulation of sync_fifo.v. I get the error:

vsim work.sync_fifo -L altera_mf# vsim -L altera_mf work.sync_fifo # Loading work.sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(83): Unresolved defparam reference to 'scfifo_component' in scfifo_component.add_ram_output_register.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(84): Unresolved defparam reference to 'scfifo_component' in scfifo_component.intended_device_family.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(85): Unresolved defparam reference to 'scfifo_component' in scfifo_component.lpm_numwords.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(86): Unresolved defparam reference to 'scfifo_component' in scfifo_component.lpm_showahead.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(87): Unresolved defparam reference to 'scfifo_component' in scfifo_component.lpm_type.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(88): Unresolved defparam reference to 'scfifo_component' in scfifo_component.lpm_width.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(89): Unresolved defparam reference to 'scfifo_component' in scfifo_component.lpm_widthu.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(90): Unresolved defparam reference to 'scfifo_component' in scfifo_component.overflow_checking.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(91): Unresolved defparam reference to 'scfifo_component' in scfifo_component.underflow_checking.# # Region: /sync_fifo# ** Error: (vsim-10000) Z:/Altera_Projects/video_prototype/sync_fifo.v(92): Unresolved defparam reference to 'scfifo_component' in scfifo_component.use_eab.# # Region: /sync_fifo

Altera_Forum · ‎02-17-2016

That implies it is using the sync_fifo_bb file as the reference for the sync_fifo - hence the Z outputs. It also now means you havent included the altera libraries properly.

Remove the _bb file from the project. This is only for copy/pasting into your code.

Altera_Forum · ‎02-17-2016

I have removed it from the project. What do I need to do besides add the "-L altera_mf" to my vsim command? I thought ModelSim-Altera came with all the Altera libraries already installed. I see a huge list in the libraries pane, and altera_mf is definitely in there.

Altera_Forum · ‎02-17-2016

Oops, that should be:

vsim sync_fifo_tb -L altera_mf_ver

Altera_Forum · ‎02-17-2016

altera_mf is the vhdl library the verilog versions are all _ver

Altera_Forum · ‎02-17-2016

Gah! Of course it is.

Thanks for all your help. It's working now!

For future people: You have to also make sure you add the library to your modelsim.ini file in the project directory. My library section looks like this:

[Library]

others = $MODEL_TECH/../modelsim.ini

; Altera Primitive libraries

;

; VHDL Section

;

; Verilog Section

;

altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf

DNguy4 · ‎12-04-2018

Hi,

I have very similar problem but I can't fix it yet. I see "U" on all outputs of my Fifo_x16. I generate the Fifo_x16 using Quartus Pro 18.1 and I use VHDL 2008. I think vsim doesn't use the right library for the simulation. Can you please tell me how to make it use the right library. I think Fifo_x16 is not part of the megafunction (mf).

Thanks